2c85bcb463
Board level pin available info: duo & duo256: NAME SPI CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP6 SPI2_SCK PWR_GPIO[23] SD1_CLK__SPI2_SCK GP7 SPI2_SDO PWR_GPIO[22] SD1_CMD__SPI2_SDO GP8 SPI2_SDI PWR_GPIO[21] SD1_D0__SPI2_SDI GP9 SPI2_CS_X PWR_GPIO[18] SD1_D3__SPI2_CS_X Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
337 lines
8.1 KiB
C
337 lines
8.1 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-03-28 qiujingbao first version
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*/
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#include "drv_spi.h"
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#include "drv_pinmux.h"
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#define DBG_TAG "drv.spi"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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static struct cv1800_spi cv1800_spi_obj[] =
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{
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#ifdef BSP_USING_SPI
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{
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.spi_id = SPI2,
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.device_name = "spi2",
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.fifo_len = SPI_TXFTLR,
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},
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#endif
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};
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static struct spi_regs *get_spi_base(uint8_t spi_id)
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{
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struct spi_regs *spi_base = NULL;
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switch (spi_id)
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{
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case SPI0:
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spi_base = (struct spi_regs *)SPI0_BASE;
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break;
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case SPI1:
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spi_base = (struct spi_regs *)SPI1_BASE;
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break;
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case SPI2:
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spi_base = (struct spi_regs *)SPI2_BASE;
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break;
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case SPI3:
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spi_base = (struct spi_regs *)SPI3_BASE;
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break;
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}
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return spi_base;
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}
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static rt_err_t drv_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
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{
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rt_err_t ret = RT_EOK;
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struct cv1800_spi *spi_dev = RT_NULL;
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uint32_t mode;
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spi_dev = (struct cv1800_spi *)(device->bus->parent.user_data);
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spi_dev->data_width = configuration->data_width;
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/* disable spi */
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spi_enable(spi_dev->reg, 0);
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/* clear irq */
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spi_clear_irq(spi_dev->reg, SPI_IRQ_MSAK);
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/* set clk */
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ret = spi_set_frequency(spi_dev->reg, configuration->max_hz);
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if (ret)
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return ret;
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/* set mode */
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ret = gen_spi_mode(configuration, &mode);
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if (ret)
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return ret;
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spi_set_mode(spi_dev->reg, mode);
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/* set cs */
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spi_enable_cs(spi_dev->reg, 0x1);
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spi_enable(spi_dev->reg, 0x1);
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mode = mmio_read_32((uintptr_t)&spi_dev->reg->spi_ctrl0);
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LOG_D("mode: %x", mode);
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mode = mmio_read_32((uintptr_t)&spi_dev->reg->spi_baudr);
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LOG_D("spi_baudr: %x", mode);
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return ret;
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}
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int hw_spi_recv(struct cv1800_spi *dev) {
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uint32_t rever;
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uint32_t tem;
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int ret;
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rever = mmio_read_32((uintptr_t)&dev->reg->spi_rxflr);
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ret = (int)rever;
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while (rever)
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{
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tem = mmio_read_32((uintptr_t)&dev->reg->spi_dr);
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if (dev->recv_buf < dev->recv_end)
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{
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if (dev->data_width == 8)
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*(uint8_t *)(dev->recv_buf) = tem;
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else
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*(uint16_t *)(dev->recv_buf) = tem;
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}
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else
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{
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return 0;
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}
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rever--;
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dev->recv_buf += dev->data_width >> 3;
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}
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return ret;
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}
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int hw_spi_send(struct cv1800_spi *dev) {
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uint32_t txflr;
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uint32_t max;
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uint16_t value;
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txflr = mmio_read_32((uintptr_t)&dev->reg->spi_txflr);
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max = dev->fifo_len - txflr;
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while (max)
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{
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if (dev->send_end - dev->send_buf)
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{
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if (dev->data_width == 8)
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value = *(uint8_t *)(dev->send_buf);
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else
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value = *(uint16_t *)(dev->send_buf);
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}
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else
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{
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return 0;
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}
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mmio_write_32((uintptr_t)&dev->reg->spi_dr, value);
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dev->send_buf += dev->data_width >> 3;
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max--;
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}
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return 0;
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}
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static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) {
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int ret = 0;
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struct cv1800_spi *spi_dev;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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spi_dev = (struct cv1800_spi *)(device->bus->parent.user_data);
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if (message->send_buf != RT_NULL)
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{
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spi_dev->send_buf = message->send_buf;
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spi_dev->send_end = (void *)((uint8_t *)spi_dev->send_buf + message->length);
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}
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if (message->recv_buf != RT_NULL)
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{
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spi_dev->recv_buf = message->recv_buf;
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spi_dev->recv_end = (void *)((uint8_t *)spi_dev->recv_buf + message->length);
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}
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/* if user use their cs */
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if (message->cs_take && device->cs_pin != PIN_NONE)
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rt_pin_write(device->cs_pin, PIN_LOW);
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if (message->send_buf)
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{
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while (spi_dev->send_buf != spi_dev->send_end)
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{
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hw_spi_send(spi_dev);
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}
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/* wait for complete */
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while (mmio_read_32((uintptr_t)&spi_dev->reg->spi_txflr)) {}
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ret = message->length;
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}
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if (message->recv_buf)
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{
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while (spi_dev->recv_buf != spi_dev->recv_end)
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{
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hw_spi_recv(spi_dev);
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}
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ret = message->length;
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}
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if (message->cs_release && device->cs_pin != PIN_NONE)
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rt_pin_write(device->cs_pin, PIN_HIGH);
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return ret;
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}
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const static struct rt_spi_ops drv_spi_ops =
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{
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drv_spi_configure,
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spixfer,
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};
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#if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO_SPINOR) || defined(BOARD_TYPE_MILKV_DUO256M) || defined(BOARD_TYPE_MILKV_DUO256M_SPINOR)
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#ifdef BSP_USING_SPI0
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static const char *pinname_whitelist_spi0_sck[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi0_sdo[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi0_sdi[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi0_cs[] = {
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NULL,
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};
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#endif
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#ifdef BSP_USING_SPI1
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static const char *pinname_whitelist_spi1_sck[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi1_sdo[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi1_sdi[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi1_cs[] = {
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NULL,
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};
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#endif
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#ifdef BSP_USING_SPI2
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static const char *pinname_whitelist_spi2_sck[] = {
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"SD1_CLK",
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NULL,
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};
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static const char *pinname_whitelist_spi2_sdo[] = {
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"SD1_CMD",
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NULL,
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};
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static const char *pinname_whitelist_spi2_sdi[] = {
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"SD1_D0",
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NULL,
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};
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static const char *pinname_whitelist_spi2_cs[] = {
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"SD1_D3",
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NULL,
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};
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#endif
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#ifdef BSP_USING_SPI3
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static const char *pinname_whitelist_spi3_sck[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi3_sdo[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi3_sdi[] = {
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NULL,
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};
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static const char *pinname_whitelist_spi3_cs[] = {
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NULL,
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};
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#endif
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#else
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#error "Unsupported board type!"
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#endif
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static void rt_hw_spi_pinmux_config()
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{
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#ifdef BSP_USING_SPI0
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pinmux_config(BSP_SPI0_SCK_PINNAME, SPI0_SCK, pinname_whitelist_spi0_sck);
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pinmux_config(BSP_SPI0_SDO_PINNAME, SPI0_SDO, pinname_whitelist_spi0_sdo);
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pinmux_config(BSP_SPI0_SDI_PINNAME, SPI0_SDI, pinname_whitelist_spi0_sdi);
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pinmux_config(BSP_SPI0_CS_PINNAME, SPI0_CS_X, pinname_whitelist_spi0_cs);
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#endif /* BSP_USING_SPI0 */
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#ifdef BSP_USING_SPI1
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pinmux_config(BSP_SPI1_SCK_PINNAME, SPI1_SCK, pinname_whitelist_spi1_sck);
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pinmux_config(BSP_SPI1_SDO_PINNAME, SPI1_SDO, pinname_whitelist_spi1_sdo);
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pinmux_config(BSP_SPI1_SDI_PINNAME, SPI1_SDI, pinname_whitelist_spi1_sdi);
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pinmux_config(BSP_SPI1_CS_PINNAME, SPI1_CS_X, pinname_whitelist_spi1_cs);
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#endif /* BSP_USING_SPI1 */
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#ifdef BSP_USING_SPI2
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pinmux_config(BSP_SPI2_SCK_PINNAME, SPI2_SCK, pinname_whitelist_spi2_sck);
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pinmux_config(BSP_SPI2_SDO_PINNAME, SPI2_SDO, pinname_whitelist_spi2_sdo);
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pinmux_config(BSP_SPI2_SDI_PINNAME, SPI2_SDI, pinname_whitelist_spi2_sdi);
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pinmux_config(BSP_SPI2_CS_PINNAME, SPI2_CS_X, pinname_whitelist_spi2_cs);
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#endif /* BSP_USING_SPI2 */
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#ifdef BSP_USING_SPI3
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pinmux_config(BSP_SPI3_SCK_PINNAME, SPI3_SCK, pinname_whitelist_spi3_sck);
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pinmux_config(BSP_SPI3_SDO_PINNAME, SPI3_SDO, pinname_whitelist_spi3_sdo);
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pinmux_config(BSP_SPI3_SDI_PINNAME, SPI3_SDI, pinname_whitelist_spi3_sdi);
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pinmux_config(BSP_SPI3_CS_PINNAME, SPI3_CS_X, pinname_whitelist_spi3_cs);
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#endif /* BSP_USING_SPI3 */
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}
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int rt_hw_spi_init(void)
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{
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rt_err_t ret = RT_EOK;
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struct spi_regs *reg = NULL;
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rt_hw_spi_pinmux_config();
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for (rt_size_t i = 0; i < sizeof(cv1800_spi_obj) / sizeof(struct cv1800_spi); i++) {
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/* set reg base addr */
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reg = get_spi_base(cv1800_spi_obj[i].spi_id);
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if (!reg)
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return -RT_ERROR;
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cv1800_spi_obj[i].reg = reg;
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cv1800_spi_obj[i].spi_bus.parent.user_data = &cv1800_spi_obj[i];
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/* register spix bus */
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ret = rt_spi_bus_register(&cv1800_spi_obj[i].spi_bus, cv1800_spi_obj[i].device_name, &drv_spi_ops);
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}
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return ret;
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}
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INIT_BOARD_EXPORT(rt_hw_spi_init);
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