400 lines
14 KiB
C
400 lines
14 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/01 Bernard The first version
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* 2018/12/27 Jesven Change irq enable/disable to cpu0
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*/
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#include <rthw.h>
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#include "tick.h"
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#include <plic.h>
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#include <clint.h>
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#include <interrupt.h>
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#define CPU_NUM 2
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#define MAX_HANDLERS IRQN_MAX
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static struct rt_irq_desc irq_desc[MAX_HANDLERS];
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static rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
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{
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rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector);
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return RT_NULL;
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}
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int rt_hw_clint_ipi_enable(void)
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{
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/* Set the Machine-Software bit in MIE */
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set_csr(mie, MIP_MSIP);
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return 0;
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}
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int rt_hw_clint_ipi_disable(void)
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{
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/* Clear the Machine-Software bit in MIE */
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clear_csr(mie, MIP_MSIP);
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return 0;
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}
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int rt_hw_plic_irq_enable(plic_irq_t irq_number)
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{
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unsigned long core_id = 0;
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/* Check parameters */
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if (PLIC_NUM_SOURCES < irq_number || 0 > irq_number)
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return -1;
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/* Get current enable bit array by IRQ number */
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uint32_t current = plic->target_enables.target[core_id].enable[irq_number / 32];
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/* Set enable bit in enable bit array */
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current |= (uint32_t)1 << (irq_number % 32);
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/* Write back the enable bit array */
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plic->target_enables.target[core_id].enable[irq_number / 32] = current;
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return 0;
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}
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int rt_hw_plic_irq_disable(plic_irq_t irq_number)
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{
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unsigned long core_id = 0;
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/* Check parameters */
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if (PLIC_NUM_SOURCES < irq_number || 0 > irq_number)
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return -1;
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/* Get current enable bit array by IRQ number */
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uint32_t current = plic->target_enables.target[core_id].enable[irq_number / 32];
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/* Clear enable bit in enable bit array */
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current &= ~((uint32_t)1 << (irq_number % 32));
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/* Write back the enable bit array */
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plic->target_enables.target[core_id].enable[irq_number / 32] = current;
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return 0;
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}
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/**
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* This function will initialize hardware interrupt
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*/
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void rt_hw_interrupt_init(void)
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{
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int idx;
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int cpuid;
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cpuid = current_coreid();
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/* Disable all interrupts for the current core. */
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for (idx = 0; idx < ((PLIC_NUM_SOURCES + 32u) / 32u); idx ++)
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plic->target_enables.target[cpuid].enable[idx] = 0;
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/* Set priorities to zero. */
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for (idx = 0; idx < PLIC_NUM_SOURCES; idx++)
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plic->source_priorities.priority[idx] = 0;
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/* Set the threshold to zero. */
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plic->targets.target[cpuid].priority_threshold = 0;
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/* init exceptions table */
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for (idx = 0; idx < MAX_HANDLERS; idx++)
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{
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rt_hw_interrupt_mask(idx);
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irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
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irq_desc[idx].param = RT_NULL;
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#ifdef RT_USING_INTERRUPT_INFO
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rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
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irq_desc[idx].counter = 0;
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#endif
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}
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/* Enable machine external interrupts. */
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set_csr(mie, MIP_MEIP);
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}
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void rt_hw_scondary_interrupt_init(void)
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{
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int idx;
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int cpuid;
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cpuid = current_coreid();
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/* Disable all interrupts for the current core. */
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for (idx = 0; idx < ((PLIC_NUM_SOURCES + 32u) / 32u); idx ++)
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plic->target_enables.target[cpuid].enable[idx] = 0;
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/* Set the threshold to zero. */
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plic->targets.target[cpuid].priority_threshold = 0;
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/* Enable machine external interrupts. */
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set_csr(mie, MIP_MEIP);
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}
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/**
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* This function will mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_mask(int vector)
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{
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rt_hw_plic_irq_disable(vector);
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}
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/**
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* This function will un-mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_umask(int vector)
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{
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plic_set_priority(vector, 1);
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rt_hw_plic_irq_enable(vector);
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}
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/**
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* This function will install a interrupt service routine to a interrupt.
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* @param vector the interrupt number
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* @param new_handler the interrupt service routine to be installed
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* @param old_handler the old interrupt service routine
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*/
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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void *param, const char *name)
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{
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rt_isr_handler_t old_handler = RT_NULL;
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if(vector < MAX_HANDLERS)
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{
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old_handler = irq_desc[vector].handler;
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if (handler != RT_NULL)
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{
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irq_desc[vector].handler = (rt_isr_handler_t)handler;
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irq_desc[vector].param = param;
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#ifdef RT_USING_INTERRUPT_INFO
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rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
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irq_desc[vector].counter = 0;
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#endif
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}
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}
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return old_handler;
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}
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RT_WEAK
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void plic_irq_handle(plic_irq_t irq)
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{
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rt_kprintf("UN-handled interrupt %d occurred!!!\n", irq);
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return ;
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}
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uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc)
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{
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/*
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* After the highest-priority pending interrupt is claimed by a target
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* and the corresponding IP bit is cleared, other lower-priority
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* pending interrupts might then become visible to the target, and so
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* the PLIC EIP bit might not be cleared after a claim. The interrupt
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* handler can check the local meip/heip/seip/ueip bits before exiting
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* the handler, to allow more efficient service of other interrupts
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* without first restoring the interrupted context and taking another
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* interrupt trap.
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*/
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if (read_csr(mip) & MIP_MEIP)
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{
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/* Get current core id */
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uint64_t core_id = current_coreid();
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/* Get primitive interrupt enable flag */
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uint64_t ie_flag = read_csr(mie);
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/* Get current IRQ num */
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uint32_t int_num = plic->targets.target[core_id].claim_complete;
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/* Get primitive IRQ threshold */
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uint32_t int_threshold = plic->targets.target[core_id].priority_threshold;
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/* Set new IRQ threshold = current IRQ threshold */
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plic->targets.target[core_id].priority_threshold = plic->source_priorities.priority[int_num];
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/* Disable software interrupt and timer interrupt */
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clear_csr(mie, MIP_MTIP | MIP_MSIP);
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if (irq_desc[int_num].handler == (rt_isr_handler_t)rt_hw_interrupt_handle)
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{
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/* default handler, route to kendryte bsp plic driver */
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plic_irq_handle(int_num);
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}
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else if (irq_desc[int_num].handler)
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{
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irq_desc[int_num].handler(int_num, irq_desc[int_num].param);
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}
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/* Perform IRQ complete */
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plic->targets.target[core_id].claim_complete = int_num;
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/* Set MPIE and MPP flag used to MRET instructions restore MIE flag */
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set_csr(mstatus, MSTATUS_MPIE | MSTATUS_MPP);
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/* Restore primitive interrupt enable flag */
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write_csr(mie, ie_flag);
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/* Restore primitive IRQ threshold */
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plic->targets.target[core_id].priority_threshold = int_threshold;
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}
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return epc;
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}
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struct exception_stack_frame
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{
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uint64_t x1;
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uint64_t x2;
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uint64_t x3;
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uint64_t x4;
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uint64_t x5;
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uint64_t x6;
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uint64_t x7;
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uint64_t x8;
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uint64_t x9;
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uint64_t x10;
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uint64_t x11;
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uint64_t x12;
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uint64_t x13;
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uint64_t x14;
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uint64_t x15;
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uint64_t x16;
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uint64_t x17;
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uint64_t x18;
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uint64_t x19;
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uint64_t x20;
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uint64_t x21;
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uint64_t x22;
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uint64_t x23;
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uint64_t x24;
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uint64_t x25;
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uint64_t x26;
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uint64_t x27;
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uint64_t x28;
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uint64_t x29;
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uint64_t x30;
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uint64_t x31;
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};
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void print_stack_frame(uintptr_t * sp)
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{
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struct exception_stack_frame * esf = (struct exception_stack_frame *)(sp+1);
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rt_kprintf("\n=================================================================\n");
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rt_kprintf("x1 (ra : Return address ) ==> 0x%08x%08x\n", esf->x1 >> 32 , esf->x1 & UINT32_MAX);
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rt_kprintf("x2 (sp : Stack pointer ) ==> 0x%08x%08x\n", esf->x2 >> 32 , esf->x2 & UINT32_MAX);
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rt_kprintf("x3 (gp : Global pointer ) ==> 0x%08x%08x\n", esf->x3 >> 32 , esf->x3 & UINT32_MAX);
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rt_kprintf("x4 (tp : Thread pointer ) ==> 0x%08x%08x\n", esf->x4 >> 32 , esf->x4 & UINT32_MAX);
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rt_kprintf("x5 (t0 : Temporary ) ==> 0x%08x%08x\n", esf->x5 >> 32 , esf->x5 & UINT32_MAX);
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rt_kprintf("x6 (t1 : Temporary ) ==> 0x%08x%08x\n", esf->x6 >> 32 , esf->x6 & UINT32_MAX);
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rt_kprintf("x7 (t2 : Temporary ) ==> 0x%08x%08x\n", esf->x7 >> 32 , esf->x7 & UINT32_MAX);
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rt_kprintf("x8 (s0/fp: Save register,frame pointer ) ==> 0x%08x%08x\n", esf->x8 >> 32 , esf->x8 & UINT32_MAX);
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rt_kprintf("x9 (s1 : Save register ) ==> 0x%08x%08x\n", esf->x9 >> 32 , esf->x9 & UINT32_MAX);
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rt_kprintf("x10(a0 : Function argument,return value) ==> 0x%08x%08x\n", esf->x10 >> 32 , esf->x10 & UINT32_MAX);
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rt_kprintf("x11(a1 : Function argument,return value) ==> 0x%08x%08x\n", esf->x11 >> 32 , esf->x11 & UINT32_MAX);
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rt_kprintf("x12(a2 : Function argument ) ==> 0x%08x%08x\n", esf->x12 >> 32 , esf->x12 & UINT32_MAX);
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rt_kprintf("x13(a3 : Function argument ) ==> 0x%08x%08x\n", esf->x13 >> 32 , esf->x13 & UINT32_MAX);
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rt_kprintf("x14(a4 : Function argument ) ==> 0x%08x%08x\n", esf->x14 >> 32 , esf->x14 & UINT32_MAX);
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rt_kprintf("x15(a5 : Function argument ) ==> 0x%08x%08x\n", esf->x15 >> 32 , esf->x15 & UINT32_MAX);
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rt_kprintf("x16(a6 : Function argument ) ==> 0x%08x%08x\n", esf->x16 >> 32 , esf->x16 & UINT32_MAX);
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rt_kprintf("x17(a7 : Function argument ) ==> 0x%08x%08x\n", esf->x17 >> 32 , esf->x17 & UINT32_MAX);
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rt_kprintf("x18(s2 : Save register ) ==> 0x%08x%08x\n", esf->x18 >> 32 , esf->x18 & UINT32_MAX);
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rt_kprintf("x19(s3 : Save register ) ==> 0x%08x%08x\n", esf->x19 >> 32 , esf->x19 & UINT32_MAX);
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rt_kprintf("x20(s4 : Save register ) ==> 0x%08x%08x\n", esf->x20 >> 32 , esf->x20 & UINT32_MAX);
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rt_kprintf("x21(s5 : Save register ) ==> 0x%08x%08x\n", esf->x21 >> 32 , esf->x21 & UINT32_MAX);
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rt_kprintf("x22(s6 : Save register ) ==> 0x%08x%08x\n", esf->x22 >> 32 , esf->x22 & UINT32_MAX);
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rt_kprintf("x23(s7 : Save register ) ==> 0x%08x%08x\n", esf->x23 >> 32 , esf->x23 & UINT32_MAX);
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rt_kprintf("x24(s8 : Save register ) ==> 0x%08x%08x\n", esf->x24 >> 32 , esf->x24 & UINT32_MAX);
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rt_kprintf("x25(s9 : Save register ) ==> 0x%08x%08x\n", esf->x25 >> 32 , esf->x25 & UINT32_MAX);
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rt_kprintf("x26(s10 : Save register ) ==> 0x%08x%08x\n", esf->x26 >> 32 , esf->x26 & UINT32_MAX);
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rt_kprintf("x27(s11 : Save register ) ==> 0x%08x%08x\n", esf->x27 >> 32 , esf->x27 & UINT32_MAX);
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rt_kprintf("x28(t3 : Temporary ) ==> 0x%08x%08x\n", esf->x28 >> 32 , esf->x28 & UINT32_MAX);
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rt_kprintf("x29(t4 : Temporary ) ==> 0x%08x%08x\n", esf->x29 >> 32 , esf->x29 & UINT32_MAX);
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rt_kprintf("x30(t5 : Temporary ) ==> 0x%08x%08x\n", esf->x30 >> 32 , esf->x30 & UINT32_MAX);
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rt_kprintf("x31(t6 : Temporary ) ==> 0x%08x%08x\n", esf->x31 >> 32 , esf->x31 & UINT32_MAX);
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rt_kprintf("=================================================================\n");
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}
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uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc, uintptr_t * sp)
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{
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int cause = mcause & CAUSE_MACHINE_IRQ_REASON_MASK;
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if (mcause & (1UL << 63))
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{
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switch (cause)
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{
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case IRQ_M_SOFT:
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{
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uint64_t core_id = current_coreid();
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clint_ipi_clear(core_id);
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rt_schedule();
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}
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break;
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case IRQ_M_EXT:
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handle_irq_m_ext(mcause, epc);
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break;
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case IRQ_M_TIMER:
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tick_isr();
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break;
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}
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}
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else
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{
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rt_thread_t tid;
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#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
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extern long list_thread();
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#endif
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rt_hw_interrupt_disable();
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tid = rt_thread_self();
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rt_kprintf("\nException:\n");
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switch (cause)
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{
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case CAUSE_MISALIGNED_FETCH:
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rt_kprintf("Instruction address misaligned");
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break;
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case CAUSE_FAULT_FETCH:
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rt_kprintf("Instruction access fault");
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break;
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case CAUSE_ILLEGAL_INSTRUCTION:
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rt_kprintf("Illegal instruction");
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break;
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case CAUSE_BREAKPOINT:
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rt_kprintf("Breakpoint");
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break;
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case CAUSE_MISALIGNED_LOAD:
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rt_kprintf("Load address misaligned");
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break;
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case CAUSE_FAULT_LOAD:
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rt_kprintf("Load access fault");
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break;
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case CAUSE_MISALIGNED_STORE:
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rt_kprintf("Store address misaligned");
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break;
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case CAUSE_FAULT_STORE:
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rt_kprintf("Store access fault");
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break;
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case CAUSE_USER_ECALL:
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rt_kprintf("Environment call from U-mode");
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break;
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case CAUSE_SUPERVISOR_ECALL:
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rt_kprintf("Environment call from S-mode");
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break;
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case CAUSE_HYPERVISOR_ECALL:
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rt_kprintf("Environment call from H-mode");
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break;
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case CAUSE_MACHINE_ECALL:
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rt_kprintf("Environment call from M-mode");
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break;
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default:
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rt_kprintf("Uknown exception : %08lX", cause);
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break;
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}
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rt_kprintf("\n");
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print_stack_frame(sp);
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rt_kprintf("exception pc => 0x%08x\n", epc);
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rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, tid->name);
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#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
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list_thread();
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#endif
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while(1);
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}
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return epc;
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}
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