444 lines
14 KiB
C
444 lines
14 KiB
C
/**************************************************************************//**
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* @file pdma.c
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* @brief PDMA driver source file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "nuc980.h"
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#include "nu_pdma.h"
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static uint8_t u32ChSelect[PDMA_CH_MAX];
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/** @addtogroup Standard_Driver Standard Driver
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@{
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*/
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/** @addtogroup PDMA_Driver PDMA Driver
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@{
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*/
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/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
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@{
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*/
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/**
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* @brief PDMA Open
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*
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* @param[in] pdma The pointer of the specified PDMA module
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*
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* @param[in] u32Mask Channel enable bits.
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*
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* @return None
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*
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* @details This function enable the PDMA channels.
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*/
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void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask)
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{
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uint32_t i;
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for (i = 0UL; i < PDMA_CH_MAX; i++)
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{
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if ((1 << i) & u32Mask)
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{
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pdma->DSCT[i].CTL = 0UL;
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u32ChSelect[i] = PDMA_MEM;
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}
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}
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pdma->CHCTL |= u32Mask;
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}
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/**
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* @brief PDMA Close
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*
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* @param[in] pdma The pointer of the specified PDMA module
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*
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* @return None
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*
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* @details This function disable all PDMA channels.
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*/
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void PDMA_Close(PDMA_T *pdma)
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{
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pdma->CHCTL = 0UL;
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}
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/**
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* @brief Set PDMA Transfer Count
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*
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* @param[in] pdma The pointer of the specified PDMA module
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* @param[in] u32Ch The selected channel
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* @param[in] u32Width Data width. Valid values are
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* - \ref PDMA_WIDTH_8
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* - \ref PDMA_WIDTH_16
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* - \ref PDMA_WIDTH_32
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* @param[in] u32TransCount Transfer count
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*
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* @return None
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*
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* @details This function set the selected channel data width and transfer count.
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*/
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void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
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{
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pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);
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pdma->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos));
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}
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/**
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* @brief Set PDMA Stride Mode
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*
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* @param[in] pdma The pointer of the specified PDMA module
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* @param[in] u32Ch The selected channel
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* @param[in] u32DestLen Destination stride count
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* @param[in] u32SrcLen Source stride count
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* @param[in] u32TransCount Transfer count
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*
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* @return None
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*
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* @details This function set the selected stride mode.
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*/
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void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount)
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{
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pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk;
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pdma->STRIDE[u32Ch].ASOCR = (u32DestLen << 16) | u32SrcLen;
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pdma->STRIDE[u32Ch].STCR = u32TransCount;
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}
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/**
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* @brief Set PDMA Transfer Address
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*
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* @param[in] pdma The pointer of the specified PDMA module
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* @param[in] u32Ch The selected channel
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* @param[in] u32SrcAddr Source address
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* @param[in] u32SrcCtrl Source control attribute. Valid values are
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* - \ref PDMA_SAR_INC
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* - \ref PDMA_SAR_FIX
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* @param[in] u32DstAddr destination address
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* @param[in] u32DstCtrl destination control attribute. Valid values are
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* - \ref PDMA_DAR_INC
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* - \ref PDMA_DAR_FIX
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*
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* @return None
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*
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* @details This function set the selected channel source/destination address and attribute.
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*/
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void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
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{
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pdma->DSCT[u32Ch].SA = u32SrcAddr;
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pdma->DSCT[u32Ch].DA = u32DstAddr;
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pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);
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pdma->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
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}
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/**
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* @brief Set PDMA Transfer Mode
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*
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* @param[in] pdma The pointer of the specified PDMA module
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* @param[in] u32Ch The selected channel
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* @param[in] u32Peripheral The selected peripheral. Valid values are
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* - \ref PDMA_MEM
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* - \ref PDMA_UART0_TX
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* - \ref PDMA_UART0_RX
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* - \ref PDMA_UART1_TX
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* - \ref PDMA_UART1_RX
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* - \ref PDMA_UART2_TX
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* - \ref PDMA_UART2_RX
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* - \ref PDMA_UART3_TX
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* - \ref PDMA_UART3_RX
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* - \ref PDMA_UART4_TX
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* - \ref PDMA_UART4_RX
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* - \ref PDMA_UART5_TX
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* - \ref PDMA_UART5_RX
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* - \ref PDMA_UART6_TX
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* - \ref PDMA_UART6_RX
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* - \ref PDMA_UART7_TX
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* - \ref PDMA_UART7_RX
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* - \ref PDMA_QSPI0_TX
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* - \ref PDMA_QSPI0_RX
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* - \ref PDMA_SPI0_TX
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* - \ref PDMA_SPI0_RX
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* - \ref PDMA_SPI1_TX
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* - \ref PDMA_SPI1_RX
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* - \ref PDMA_UART8_TX
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* - \ref PDMA_UART8_RX
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* - \ref PDMA_UART9_TX
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* - \ref PDMA_UART9_RX
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* - \ref PDMA_I2C0_TX
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* - \ref PDMA_I2C0_RX
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* - \ref PDMA_I2C1_TX
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* - \ref PDMA_I2C1_RX
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* - \ref PDMA_I2C2_TX
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* - \ref PDMA_I2C2_RX
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* - \ref PDMA_I2C3_TX
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* - \ref PDMA_I2C3_RX
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* - \ref PDMA_TIMER0
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* - \ref PDMA_TIMER1
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* - \ref PDMA_TIMER2
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* - \ref PDMA_TIMER3
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* - \ref PDMA_TIMER4
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* - \ref PDMA_TIMER5
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* @param[in] u32ScatterEn Scatter-gather mode enable
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* @param[in] u32DescAddr Scatter-gather descriptor address
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*
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* @return None
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*
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* @details This function set the selected channel transfer mode. Include peripheral setting.
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*/
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void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
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{
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u32ChSelect[u32Ch] = u32Peripheral;
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switch (u32Ch)
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{
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case 0ul:
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pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
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break;
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case 1ul:
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pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
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break;
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case 2ul:
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pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
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break;
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case 3ul:
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pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
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break;
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case 4ul:
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pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
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break;
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case 5ul:
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pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
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break;
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case 6ul:
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pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
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break;
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case 7ul:
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pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
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break;
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case 8ul:
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pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral;
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break;
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case 9ul:
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pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos);
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break;
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default:
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break;
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}
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if (u32ScatterEn)
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{
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pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
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pdma->DSCT[u32Ch].NEXT = u32DescAddr - (pdma->SCATBA);
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}
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else
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{
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pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
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}
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}
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/**
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* @brief Set PDMA Burst Type and Size
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*
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* @param[in] pdma The pointer of the specified PDMA module
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* @param[in] u32Ch The selected channel
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* @param[in] u32BurstType Burst mode or single mode. Valid values are
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* - \ref PDMA_REQ_SINGLE
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* - \ref PDMA_REQ_BURST
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* @param[in] u32BurstSize Set the size of burst mode. Valid values are
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* - \ref PDMA_BURST_128
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* - \ref PDMA_BURST_64
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* - \ref PDMA_BURST_32
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* - \ref PDMA_BURST_16
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* - \ref PDMA_BURST_8
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* - \ref PDMA_BURST_4
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* - \ref PDMA_BURST_2
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* - \ref PDMA_BURST_1
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*
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* @return None
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*
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* @details This function set the selected channel burst type and size.
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*/
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void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
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{
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pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);
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pdma->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
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}
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/**
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* @brief Enable timeout function
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*
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* @param[in] pdma The pointer of the specified PDMA module
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*
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* @param[in] u32Mask Channel enable bits.
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*
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* @return None
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*
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* @details This function enable timeout function of the selected channel(s).
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*/
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void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask)
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{
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pdma->TOUTEN |= u32Mask;
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}
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/**
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* @brief Disable timeout function
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*
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* @param[in] pdma The pointer of the specified PDMA module
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*
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* @param[in] u32Mask Channel enable bits.
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*
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* @return None
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*
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* @details This function disable timeout function of the selected channel(s).
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*/
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void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask)
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{
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pdma->TOUTEN &= ~u32Mask;
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}
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/**
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* @brief Set PDMA Timeout Count
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*
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* @param[in] pdma The pointer of the specified PDMA module
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* @param[in] u32Ch The selected channel,
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* @param[in] u32OnOff Enable/disable time out function
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* @param[in] u32TimeOutCnt Timeout count
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*
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* @return None
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*
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* @details This function set the timeout count.
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*/
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void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
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{
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switch (u32Ch)
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{
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case 0ul:
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pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
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break;
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case 1ul:
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pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
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break;
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case 2ul:
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pdma->TOC2_3 = (pdma->TOC2_3 & ~PDMA_TOC2_3_TOC2_Msk) | u32TimeOutCnt;
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break;
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case 3ul:
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pdma->TOC2_3 = (pdma->TOC2_3 & ~PDMA_TOC2_3_TOC3_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
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break;
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case 4ul:
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pdma->TOC4_5 = (pdma->TOC4_5 & ~PDMA_TOC4_5_TOC4_Msk) | u32TimeOutCnt;
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break;
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case 5ul:
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pdma->TOC4_5 = (pdma->TOC4_5 & ~PDMA_TOC4_5_TOC5_Msk) | (u32TimeOutCnt << PDMA_TOC4_5_TOC5_Pos);
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break;
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case 6ul:
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pdma->TOC6_7 = (pdma->TOC6_7 & ~PDMA_TOC6_7_TOC6_Msk) | u32TimeOutCnt;
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break;
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case 7ul:
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pdma->TOC6_7 = (pdma->TOC6_7 & ~PDMA_TOC6_7_TOC7_Msk) | (u32TimeOutCnt << PDMA_TOC6_7_TOC7_Pos);
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break;
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case 8ul:
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pdma->TOC8_9 = (pdma->TOC8_9 & ~PDMA_TOC8_9_TOC8_Msk) | u32TimeOutCnt;
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break;
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case 9ul:
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pdma->TOC8_9 = (pdma->TOC8_9 & ~PDMA_TOC8_9_TOC9_Msk) | (u32TimeOutCnt << PDMA_TOC8_9_TOC9_Pos);
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break;
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default:
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break;
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}
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if (u32OnOff)
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pdma->TOUTEN |= (1 << u32Ch);
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else
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pdma->TOUTEN &= ~(1 << u32Ch);
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}
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/**
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* @brief Trigger PDMA
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*
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* @param[in] pdma The pointer of the specified PDMA module
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* @param[in] u32Ch The selected channel
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*
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* @return None
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*
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* @details This function trigger the selected channel.
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*/
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void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch)
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{
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if (u32ChSelect[u32Ch] == PDMA_MEM)
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{
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pdma->SWREQ = (1ul << u32Ch);
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}
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else {}
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}
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/**
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* @brief Enable Interrupt
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*
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* @param[in] pdma The pointer of the specified PDMA module
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* @param[in] u32Ch The selected channel
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* @param[in] u32Mask The Interrupt Type. Valid values are
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* - \ref PDMA_INT_TRANS_DONE
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* - \ref PDMA_INT_TEMPTY
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* - \ref PDMA_INT_TIMEOUT
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*
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* @return None
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*
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* @details This function enable the selected channel interrupt.
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*/
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void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask)
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{
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switch (u32Mask)
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{
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case PDMA_INT_TRANS_DONE:
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pdma->INTEN |= (1ul << u32Ch);
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break;
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case PDMA_INT_TEMPTY:
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pdma->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk;
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break;
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case PDMA_INT_TIMEOUT:
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pdma->TOUTIEN |= (1ul << u32Ch);
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break;
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default:
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break;
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}
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}
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/**
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* @brief Disable Interrupt
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*
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* @param[in] pdma The pointer of the specified PDMA module
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* @param[in] u32Ch The selected channel
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* @param[in] u32Mask The Interrupt Type. Valid values are
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* - \ref PDMA_INT_TRANS_DONE
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* - \ref PDMA_INT_TEMPTY
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* - \ref PDMA_INT_TIMEOUT
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*
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* @return None
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*
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* @details This function disable the selected channel interrupt.
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*/
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void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask)
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{
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switch (u32Mask)
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{
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case PDMA_INT_TRANS_DONE:
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pdma->INTEN &= ~(1ul << u32Ch);
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break;
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case PDMA_INT_TEMPTY:
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pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk;
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break;
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case PDMA_INT_TIMEOUT:
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pdma->TOUTIEN &= ~(1ul << u32Ch);
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break;
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default:
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break;
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}
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}
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/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group PDMA_Driver */
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/*@}*/ /* end of group Standard_Driver */
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