xiaoguang_ma 16f6157b1e [bsp] faster startup for cortex-a ... If the application defines dozens of global variables, the speed of clearing the bss segment will be slower. Because icache can be enabled before the mmu enabled. Therefore, in order to speed up the process of clearing the BSS segment, enable icache needs to be put ahead.		2022-11-25 18:04:35 +09:00
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aarch64	uniform code writing-disable interrupt	2022-04-20 14:22:43 +08:00
arc	[asm] 解决tab和空格混用的问题	2022-01-20 20:57:35 +08:00
arm	[bsp] faster startup for cortex-a	2022-11-25 18:04:35 +09:00
avr32	替换RTThread旧版文件头注释版权声明 (#5774)	2022-04-05 19:34:30 +08:00
blackfin	替换RTThread旧版文件头注释版权声明 (#5774)	2022-04-05 19:34:30 +08:00
c-sky	[libcpu] auto formatted	2021-03-27 17:51:56 +08:00
ia32	[asm] 解决tab和空格混用的问题	2022-01-20 20:57:35 +08:00
m16c	替换RTThread旧版文件头注释版权声明 (#5774)	2022-04-05 19:34:30 +08:00
mips	uniform code writing-disable interrupt	2022-04-20 14:22:43 +08:00
nios	替换RTThread旧版文件头注释版权声明 (#5774)	2022-04-05 19:34:30 +08:00
ppc	uniform code writing-disable interrupt	2022-04-20 14:22:43 +08:00
risc-v	Add BSP for HPM6750EVK and HPM6750EVKMINI (#6374)	2022-09-06 00:48:16 -04:00
rx	替换RTThread旧版文件头注释版权声明 (#5774)	2022-04-05 19:34:30 +08:00
sim	优化bsp/simulator自动初始化 (#5634)	2022-03-08 12:03:41 +08:00
sparc-v8	[Scons] 将GCC判断条件改为列表方式，方便后续增加新的编译工具链	2022-06-09 07:01:59 +08:00
ti-dsp	[bsp][c28x] add support to not disable global interrupt in context-switch to enable zero-latency isr for critical interrupts.	2022-10-19 23:41:13 -04:00
unicore32	uniform code writing-disable interrupt	2022-04-20 14:22:43 +08:00
v850	替换RTThread旧版文件头注释版权声明 (#5774)	2022-04-05 19:34:30 +08:00
xilinx	替换RTThread旧版文件头注释版权声明 (#5774)	2022-04-05 19:34:30 +08:00
Kconfig	支持只运行在安全模式下 (#6115)	2022-06-29 14:08:57 +08:00
SConscript	[libcpu] Fix the build directory issue	2019-03-26 13:36:01 +00:00