864 lines
30 KiB
C
864 lines
30 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fpcie.c
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* Date: 2022-02-10 14:55:11
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* LastEditTime: 2022-02-18 08:59:28
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* Description: This files is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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*/
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/***************************** Include Files *********************************/
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#include "fpcie.h"
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#include "fpcie_hw.h"
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#include "fpcie_common.h"
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#include "fparameters.h"
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#include "fkernel.h"
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#include <stdio.h>
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#include <string.h>
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#include "fdebug.h"
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#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
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#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
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/***************** Macros (Inline Functions) Definitions *********************/
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#define FPCIE_DEBUG_TAG "FPCIE"
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#define FPCIE_ERROR(format, ...) FT_DEBUG_PRINT_E(FPCIE_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FPCIE_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FPCIE_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FPCIE_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FPCIE_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FPCIE_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FPCIE_DEBUG_TAG, format, ##__VA_ARGS__)
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/************************** Variable Definitions *****************************/
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extern int FPcieEpCleanBar(FPcie *instance_p, u32 peu_num, u32 bar_num) ;
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static void FPcieShowRegion(const char *name, struct FPcieRegion *region)
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{
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FPCIE_DEBUG_I("PCI Autoconfig: Bus %s region: [%llx-%llx],\n"
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"\t\tPhysical Memory [%llx-%llx]", name,
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(unsigned long long)region->bus_start,
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(unsigned long long)(region->bus_start + region->size - 1),
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(unsigned long long)region->phys_start,
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(unsigned long long)(region->phys_start + region->size - 1));
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FPCIE_DEBUG_I("bus_lower is %llx ", (unsigned long long)region->bus_lower) ;
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}
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/**
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* @name: FPcieRegionConfigInit
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* @msg: 初始化PEU 用于分配的地址空间
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* @param {FPcie} *instance_p is a pointer to the FPcie instance.
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* @param {FPcieRegion} *regs 地址空间对应的指针
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* @param {u32} regs_num 传入regs 结构体的数量
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*/
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//用于资源初始化到instance_p中
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static void FPcieRegionConfigInit(FPcie *instance_p, struct FPcieRegion *regs, u32 regs_num)
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{
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u32 i ;
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for (i = 0; i < regs_num; i++)
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{
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switch (regs[i].flags)
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{
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case FPCIE_REGION_IO:
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memset(&instance_p->mem_io, 0, sizeof(struct FPcieRegion)) ;
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memcpy(&instance_p->mem_io, regs, sizeof(struct FPcieRegion)) ;
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instance_p->mem_io.exist_flg = FPCIE_REGION_EXIST_FLG ;
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instance_p->mem_io.bus_lower = instance_p->mem_io.phys_start;
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FPcieShowRegion("I/O", &instance_p->mem_io);
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break;
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case FPCIE_REGION_MEM:
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memset(&instance_p->mem, 0, sizeof(struct FPcieRegion)) ;
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memcpy(&instance_p->mem, regs, sizeof(struct FPcieRegion)) ;
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instance_p->mem.exist_flg = FPCIE_REGION_EXIST_FLG ;
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instance_p->mem.bus_lower = instance_p->mem.phys_start;
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FPcieShowRegion("Memory", &instance_p->mem);
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break;
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case (PCI_REGION_PREFETCH|FPCIE_REGION_MEM):
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memset(&instance_p->mem_prefetch, 0, sizeof(struct FPcieRegion)) ;
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memcpy(&instance_p->mem_prefetch, regs, sizeof(struct FPcieRegion)) ;
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instance_p->mem_prefetch.exist_flg = FPCIE_REGION_EXIST_FLG ;
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instance_p->mem_prefetch.bus_lower = instance_p->mem_prefetch.phys_start;
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FPcieShowRegion("Prefetchable Mem", &instance_p->mem_prefetch);
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break;
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default:
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break;
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}
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}
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}
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/**
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* @name: FPcieCfgInitialize
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* @msg: This function initializes the config space and PCIe bridge.
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* @param {FPcie} *instance_p is a pointer to the FPcie instance.
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* @param {FPcieConfig} *config_p pointer to FPcieConfig instrance Pointer.
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* @return FError
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*/
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FError FPcieCfgInitialize(FPcie *instance_p, FPcieConfig *config_p) //用于从全局配置数据中获取数据，初始化instance_p
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{
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fsize_t i;
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struct FPcieRegion mem_region = {0} ;
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struct FPcieRegion prefetch_region = {0} ;
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struct FPcieRegion io_region = {0} ;
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/* Assert arguments */
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FASSERT(instance_p != NULL);
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FASSERT(config_p != NULL);
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/* Clear instance memory and make copy of configuration */
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memset(instance_p, 0, sizeof(FPcie));
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memcpy(&instance_p->config, config_p, sizeof(FPcieConfig));
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/* 为枚举过程中，涉及的配置空间提供地址划分 */
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/* mem32 地址 */ //使用获取到的硬件信息，来初始化mem32
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mem_region.phys_start = instance_p->config.npmem_base_addr ;
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mem_region.bus_start = instance_p->config.npmem_base_addr ;
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mem_region.size = instance_p->config.npmem_size ;
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mem_region.flags = FPCIE_REGION_MEM ;
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/* mem64 地址 */ //使用获取到的硬件信息，来初始化mem64
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prefetch_region.phys_start = instance_p->config.pmem_base_addr ;
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prefetch_region.bus_start = instance_p->config.pmem_base_addr ;
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prefetch_region.size = instance_p->config.pmem_size ;
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prefetch_region.flags = (PCI_REGION_PREFETCH | FPCIE_REGION_MEM);
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/* memio 地址 */ //使用获取到的硬件信息，来初始化io
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io_region.phys_start = instance_p->config.io_base_addr ;
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io_region.bus_start = instance_p->config.io_base_addr ;
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io_region.size = instance_p->config.io_size ;
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io_region.flags = FPCIE_REGION_IO;
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/* scaned bdf array clean */
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instance_p->scaned_bdf_count = 0;
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FPcieRegionConfigInit(instance_p, &mem_region, 1) ;
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#if defined(__aarch64__)
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FPcieRegionConfigInit(instance_p, &prefetch_region, 1) ;
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#endif
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FPcieRegionConfigInit(instance_p, &io_region, 1) ;
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instance_p->is_ready = FT_COMPONENT_IS_READY;
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/* 关闭当前所有misc 中断 */
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// FPcieMiscIrqDisable(instance_p, FPCIE_PEU0_C0);
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// FPcieMiscIrqDisable(instance_p, FPCIE_PEU0_C1);
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// FPcieMiscIrqDisable(instance_p, FPCIE_PEU0_C2);
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// FPcieMiscIrqDisable(instance_p, FPCIE_PEU1_C0);
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// FPcieMiscIrqDisable(instance_p, FPCIE_PEU1_C1);
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// FPcieMiscIrqDisable(instance_p, FPCIE_PEU1_C2);
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/* 清空ep模式下所有配置地址 */
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// for (i = 0; i <= FPCIE_PEU1_C2; i++)
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// {
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// /* code */
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// FPcieEpCleanBar(instance_p, i, FPCIE_BAR_0);
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// FPcieEpCleanBar(instance_p, i, FPCIE_BAR_1);
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// FPcieEpCleanBar(instance_p, i, FPCIE_BAR_2);
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// FPcieEpCleanBar(instance_p, i, FPCIE_BAR_3);
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// FPcieEpCleanBar(instance_p, i, FPCIE_BAR_4);
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// FPcieEpCleanBar(instance_p, i, FPCIE_BAR_5);
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// }
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return (FT_SUCCESS);
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}
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u32 FPcieFindCapability(FPcie *instance_p, u32 bdf, u32 cid_type, u32 cid, u32 *cid_offset)
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{
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u32 reg_value;
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u32 next_cap_offset;
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//u32 ret;
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if (cid_type == PCIE_CAP)
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{
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/* Serach in PCIe configuration space */
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FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, FPCIE_CAPABILITY_LIST, ®_value);
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if (reg_value == 0xffffffff)
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return -1;
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next_cap_offset = (reg_value & 0xff);
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while (next_cap_offset)
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{
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FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, next_cap_offset, ®_value);
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if ((reg_value & 0xff) == cid)
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{
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*cid_offset = next_cap_offset;
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return 0;
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}
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next_cap_offset = ((reg_value >> 8) & 0xff);
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}
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}
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else if (cid_type == PCIE_ECAP)
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{
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/* Serach in PCIe extended configuration space */
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next_cap_offset = FPCIE_ECAP_START;
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while (next_cap_offset)
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{
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FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, next_cap_offset, ®_value);
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if ((reg_value & 0xffff) == cid)
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{
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*cid_offset = next_cap_offset;
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return 0;
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}
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next_cap_offset = ((reg_value >> 20) & 0xfff);
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}
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}
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/* The capability was not found */
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return -1;
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}
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const char *FPcieClassStr(u8 class)
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{
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switch (class)
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{
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case FPCI_CLASS_NOT_DEFINED:
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return "Build before PCI Rev2.0";
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break;
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case FPCI_BASE_CLASS_STORAGE:
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return "Mass storage controller";
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break;
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case FPCI_BASE_CLASS_NETWORK:
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return "Network controller";
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break;
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case FPCI_BASE_CLASS_DISPLAY:
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return "Display controller";
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break;
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case FPCI_BASE_CLASS_MULTIMEDIA:
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return "Multimedia device";
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break;
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case FPCI_BASE_CLASS_MEMORY:
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return "Memory controller";
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break;
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case FPCI_BASE_CLASS_BRIDGE:
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return "Bridge device";
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break;
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case FPCI_BASE_CLASS_COMMUNICATION:
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return "Simple comm. controller";
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break;
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case FPCI_BASE_CLASS_SYSTEM:
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return "Base system peripheral";
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break;
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case FPCI_BASE_CLASS_INPUT:
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return "Input device";
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break;
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case FPCI_BASE_CLASS_DOCKING:
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return "Docking station";
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break;
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case FPCI_BASE_CLASS_PROCESSOR:
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return "Processor";
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break;
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case FPCI_BASE_CLASS_SERIAL:
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return "Serial bus controller";
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break;
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case FPCI_BASE_CLASS_INTELLIGENT:
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return "Intelligent controller";
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break;
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case FPCI_BASE_CLASS_SATELLITE:
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return "Satellite controller";
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break;
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case FPCI_BASE_CLASS_CRYPT:
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return "Cryptographic device";
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break;
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case FPCI_BASE_CLASS_SIGNAL_PROCESSING:
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return "DSP";
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break;
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case FPCI_CLASS_OTHERS:
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return "Does not fit any class";
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break;
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default:
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return "???";
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break;
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};
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}
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void FPcieAutoRegionAlign(struct FPcieRegion *res, pci_size_t size)
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{
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res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
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}
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int FPcieAutoRegionAllocate(struct FPcieRegion *res, pci_size_t size,
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pci_addr_t *bar, bool supports_64bit)
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{
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pci_addr_t addr;
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if (!res)
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{
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printf("No resource\n");
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goto error;
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}
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addr = ((res->bus_lower - 1) | (size - 1)) + 1;
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if (addr - res->bus_start + size > res->size)
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{
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printf("No room in resource");
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goto error;
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}
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if (upper_32_bits(addr) && !supports_64bit)
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{
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printf("Cannot assign 64-bit address to 32-bit-only resource\n");
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goto error;
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}
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res->bus_lower = addr + size;
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//printf("address=0x%llx bus_lower=0x%llx\n", (unsigned long long)addr,
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// (unsigned long long)res->bus_lower);
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*bar = addr;
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return 0;
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error:
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*bar = (pci_addr_t) -1;
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return -1;
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}
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void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num,
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struct FPcieRegion *mem,
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struct FPcieRegion *prefetch, struct FPcieRegion *io,
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bool enum_only)
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{
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u32 bar_response;
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pci_size_t bar_size;
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u16 cmdstat = 0;
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int bar, bar_nr = 0;
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u8 header_type;
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int rom_addr;
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pci_addr_t bar_value;
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struct FPcieRegion *bar_res = NULL;
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int found_mem64 = 0;
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u16 class;
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FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_COMMAND_REG, &cmdstat);
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cmdstat = (cmdstat & ~(FPCIE_COMMAND_IO | FPCIE_COMMAND_MEMORY)) |
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FPCIE_COMMAND_MASTER;
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for (bar = FPCIE_BASE_ADDRESS_0;
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bar < FPCIE_BASE_ADDRESS_0 + (bars_num * 4); bar += 4)
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{
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/* Tickle the BAR and get the response */
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if (!enum_only)
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FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, bar, 0xffffffff);
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FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, bar, &bar_response);
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/* If BAR is not implemented go to the next BAR */
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if (!bar_response)
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continue;
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found_mem64 = 0;
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/* Check the BAR type and set our address mask */
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if (bar_response & FPCIE_BASE_ADDRESS_SPACE)
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{
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bar_size = ((~(bar_response & FPCIE_BASE_ADDRESS_IO_MASK))
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& 0xffff) + 1;
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if (!enum_only)
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bar_res = io;
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//printf("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
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// bar_nr, (unsigned long long)bar_size);
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}
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else
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{
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if ((bar_response & FPCIE_BASE_ADDRESS_MEM_TYPE_MASK) ==
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FPCIE_BASE_ADDRESS_MEM_TYPE_64)
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{
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u32 bar_response_upper;
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u64 bar64;
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if (!enum_only)
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{
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FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, bar + 4, 0xffffffff);
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}
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FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, bar + 4, &bar_response_upper);
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bar64 = ((u64)bar_response_upper << 32) |
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bar_response;
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bar_size = ~(bar64 & FPCIE_BASE_ADDRESS_MEM_MASK)
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+ 1;
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if (!enum_only)
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found_mem64 = 1;
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}
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else
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{
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bar_size = (u32)(~(bar_response &
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FPCIE_BASE_ADDRESS_MEM_MASK) + 1);
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}
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if (!enum_only)
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{
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if ((prefetch->exist_flg & FPCIE_REGION_EXIST_FLG) & (bar_response &
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FPCIE_BASE_ADDRESS_MEM_PREFETCH))
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{
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bar_res = prefetch;
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}
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else
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{
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bar_res = mem;
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}
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}
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//printf("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
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// bar_nr, bar_res == prefetch ? "Prf" : "Mem",
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// (unsigned long long)bar_size);
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}
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if (!enum_only && FPcieAutoRegionAllocate(bar_res, bar_size,
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&bar_value,
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found_mem64) == 0)
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{
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/* Write it out and update our limit */
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FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, bar, (u32)bar_value);
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if (found_mem64)
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{
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bar += 4;
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#ifdef CONFIG_SYS_PCI_64BIT
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FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, bar, (u32)(bar_value >> 32));
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#else
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/*
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* If we are a 64-bit decoder then increment to
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* the upper 32 bits of the bar and force it to
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* locate in the lower 4GB of memory.
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*/
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FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, bar, 0x00000000);
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#endif
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}
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}
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cmdstat |= (bar_response & FPCIE_BASE_ADDRESS_SPACE) ?
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FPCIE_COMMAND_IO : FPCIE_COMMAND_MEMORY;
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//printf("\n");
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bar_nr++;
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}
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if (!enum_only)
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{
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/* Configure the expansion ROM address */
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FPcieEcamReadConfig8bit(instance_p->config.ecam, bdf, FPCIE_HEADER_TYPE_REG, &header_type);
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header_type &= 0x7f;
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if (header_type != FPCIE_HEADER_TYPE_CARDBUS)
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{
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rom_addr = (header_type == FPCIE_HEADER_TYPE_NORMAL) ?
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FPCIE_ROM_ADDRESS : FPCIE_ROM_ADDRESS1;
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FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, rom_addr, 0xfffffffe);
|
||
FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, rom_addr, &bar_response);
|
||
if (bar_response)
|
||
{
|
||
bar_size = -(bar_response & ~1);
|
||
//printf("PCI Autoconfig: ROM, size=%#x, ",
|
||
// (unsigned int)bar_size);
|
||
if (FPcieAutoRegionAllocate(mem, bar_size,
|
||
&bar_value,
|
||
false) == 0)
|
||
{
|
||
FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, rom_addr, bar_value);
|
||
|
||
}
|
||
cmdstat |= FPCIE_COMMAND_MEMORY;
|
||
//printf("\n");
|
||
}
|
||
}
|
||
}
|
||
|
||
/* PCI_COMMAND_IO must be set for VGA device */
|
||
FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCI_CLASS_DEVICE_REG, &class);
|
||
if (class == FPCI_CLASS_DISPLAY_VGA)
|
||
cmdstat |= FPCIE_COMMAND_IO;
|
||
|
||
FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_COMMAND_REG, cmdstat);
|
||
FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_CACHE_LINE_SIZE_REG,
|
||
CONFIG_SYS_PCI_CACHE_LINE_SIZE);
|
||
FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_LATENCY_TIMER_REG, 0x80);
|
||
}
|
||
|
||
void FPcieAutoPrescanSetupBridge(FPcie *instance_p, u32 bdf, int sub_bus)
|
||
{
|
||
struct FPcieRegion *pci_mem;
|
||
struct FPcieRegion *pci_prefetch;
|
||
struct FPcieRegion *pci_io;
|
||
u16 cmdstat, prefechable_64;
|
||
|
||
pci_mem = &(instance_p->mem);
|
||
pci_prefetch = &(instance_p->mem_prefetch);
|
||
pci_io = &(instance_p->mem_io);
|
||
|
||
FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_COMMAND_REG, &cmdstat) ;
|
||
FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_BASE_REG, &prefechable_64) ;
|
||
prefechable_64 &= FPCIE_PREF_RANGE_TYPE_MASK;
|
||
|
||
/* Configure bus number registers *///暂时只有一个pcie配置空间的做法，如果多个pci配置空间，则需当前bus减去该配置空间对应设备的起始bus号
|
||
FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_PRIMARY_BUS_REG, FPCIE_BUS(bdf));
|
||
FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_SECONDARY_BUS_REG, sub_bus);
|
||
FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_SUBORDINATE_BUS_REG, 0xff);
|
||
|
||
if (pci_mem->exist_flg & FPCIE_REGION_EXIST_FLG)
|
||
{
|
||
/* Round memory allocator to 1MB boundary */
|
||
FPcieAutoRegionAlign(pci_mem, 0x100000);
|
||
|
||
/*
|
||
* Set up memory and I/O filter limits, assume 32-bit
|
||
* I/O space
|
||
*/
|
||
FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_MEMORY_BASE_REG,
|
||
(pci_mem->bus_lower & 0xfff00000) >> 16);
|
||
|
||
cmdstat |= FPCIE_COMMAND_MEMORY;
|
||
}
|
||
|
||
if (pci_prefetch->exist_flg & FPCIE_REGION_EXIST_FLG)
|
||
{
|
||
/* Round memory allocator to 1MB boundary */
|
||
FPcieAutoRegionAlign(pci_prefetch, 0x100000);
|
||
|
||
/*
|
||
* Set up memory and I/O filter limits, assume 32-bit
|
||
* I/O space
|
||
*/
|
||
FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_BASE_REG,
|
||
(pci_prefetch->bus_lower & 0xfff00000) >> 16);
|
||
|
||
if (prefechable_64 == FPCIE_PREF_RANGE_TYPE_64)
|
||
#ifdef CONFIG_SYS_PCI_64BIT
|
||
FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, FPCIE_PREF_BASE_UPPER32_REG,
|
||
pci_prefetch->bus_lower >> 32);
|
||
#else
|
||
FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, FPCIE_PREF_BASE_UPPER32_REG,
|
||
0x0);
|
||
#endif
|
||
|
||
cmdstat |= FPCIE_COMMAND_MEMORY;
|
||
}
|
||
else
|
||
{
|
||
/* We don't support prefetchable memory for now, so disable */
|
||
FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_BASE_REG, 0x1000);
|
||
FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_LIMIT_REG, 0x0);
|
||
if (prefechable_64 == FPCIE_PREF_RANGE_TYPE_64)
|
||
{
|
||
FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_BASE_UPPER32_REG, 0x0);
|
||
FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_LIMIT_UPPER32_REG, 0x0);
|
||
}
|
||
}
|
||
|
||
if (pci_io->exist_flg & FPCIE_REGION_EXIST_FLG)
|
||
{
|
||
/* Round I/O allocator to 4KB boundary */
|
||
FPcieAutoRegionAlign(pci_io, 0x1000);
|
||
|
||
FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_IO_BASE_REG,
|
||
(pci_io->bus_lower & 0x0000f000) >> 8);
|
||
FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_IO_BASE_UPPER16_REG,
|
||
(pci_io->bus_lower & 0xffff0000) >> 16);
|
||
|
||
cmdstat |= FPCIE_COMMAND_IO;
|
||
}
|
||
|
||
/* Enable memory and I/O accesses, enable bus master */
|
||
FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_COMMAND_REG, cmdstat | FPCIE_COMMAND_MASTER);
|
||
}
|
||
|
||
|
||
void FPcieAutoPostscanSetupBridge(FPcie *instance_p, u32 bdf, int sub_bus)
|
||
{
|
||
struct FPcieRegion *pci_mem;
|
||
struct FPcieRegion *pci_prefetch;
|
||
struct FPcieRegion *pci_io;
|
||
|
||
pci_mem = &(instance_p->mem);
|
||
pci_prefetch = &(instance_p->mem_prefetch);
|
||
pci_io = &(instance_p->mem_io);
|
||
|
||
/* Configure bus number registers */
|
||
FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_SUBORDINATE_BUS_REG, sub_bus);//配置一下subordinate-bus，可能在固件下不一定必须用
|
||
|
||
if (pci_mem->exist_flg & FPCIE_REGION_EXIST_FLG)
|
||
{
|
||
/* Round memory allocator to 1MB boundary */
|
||
FPcieAutoRegionAlign(pci_mem, 0x100000);
|
||
|
||
FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_MEMORY_LIMIT_REG, (pci_mem->bus_lower - 1) >> 16);
|
||
}
|
||
|
||
if (pci_prefetch->exist_flg & FPCIE_REGION_EXIST_FLG)
|
||
{
|
||
u16 prefechable_64;
|
||
|
||
FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_LIMIT_REG, &prefechable_64);
|
||
prefechable_64 &= FPCIE_PREF_RANGE_TYPE_MASK;
|
||
|
||
/* Round memory allocator to 1MB boundary */
|
||
FPcieAutoRegionAlign(pci_prefetch, 0x100000);
|
||
|
||
FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_PREF_MEMORY_LIMIT_REG, (pci_prefetch->bus_lower - 1) >> 16);
|
||
if (prefechable_64 == FPCIE_PREF_RANGE_TYPE_64)
|
||
#ifdef CONFIG_SYS_PCI_64BIT
|
||
|
||
FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, FPCIE_PREF_LIMIT_UPPER32_REG,
|
||
(pci_prefetch->bus_lower - 1) >> 32);
|
||
#else
|
||
FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, FPCIE_PREF_LIMIT_UPPER32_REG, 0x0);
|
||
#endif
|
||
}
|
||
|
||
if (pci_io->exist_flg & FPCIE_REGION_EXIST_FLG)
|
||
{
|
||
/* Round I/O allocator to 4KB boundary */
|
||
FPcieAutoRegionAlign(pci_io, 0x1000);
|
||
|
||
FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_IO_LIMIT_REG,
|
||
((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
|
||
FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_IO_LIMIT_UPPER16_REG,
|
||
((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
|
||
}
|
||
}
|
||
|
||
|
||
int FPcieHoseProbeBus(FPcie *instance_p, u32 bdf)
|
||
{
|
||
int sub_bus;
|
||
int ret;
|
||
|
||
instance_p->bus_max = instance_p->bus_max + 1;
|
||
|
||
sub_bus = instance_p->bus_max;
|
||
|
||
FPcieAutoPrescanSetupBridge(instance_p, bdf, sub_bus);
|
||
|
||
FPcieScanBus(instance_p, sub_bus, bdf);
|
||
|
||
sub_bus = instance_p->bus_max;
|
||
FPcieAutoPostscanSetupBridge(instance_p, bdf, sub_bus);
|
||
|
||
return sub_bus;
|
||
}
|
||
|
||
/*
|
||
* HJF: Changed this to return int. I think this is required
|
||
* to get the correct result when scanning bridges
|
||
*/
|
||
int FPcieAutoConfigDevice(FPcie *instance_p, u32 bdf)
|
||
{
|
||
u16 class = 0;
|
||
|
||
struct FPcieRegion *pci_mem;
|
||
struct FPcieRegion *pci_prefetch;
|
||
struct FPcieRegion *pci_io;
|
||
|
||
bool enum_only = false;
|
||
|
||
int n;
|
||
|
||
#ifdef CONFIG_PCI_ENUM_ONLY
|
||
enum_only = true;
|
||
#endif
|
||
|
||
pci_mem = &(instance_p->mem);
|
||
pci_prefetch = &(instance_p->mem_prefetch);
|
||
pci_io = &(instance_p->mem_io);
|
||
|
||
FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_CLASS_DEVICE_REG, &class) ;//读取classcode编号
|
||
|
||
switch (class)
|
||
{
|
||
case FPCI_CLASS_BRIDGE_PCI:
|
||
FPcieAutoSetupDevice(instance_p, bdf, 2, pci_mem, pci_prefetch, pci_io,
|
||
enum_only);
|
||
|
||
n = FPcieHoseProbeBus(instance_p, bdf);
|
||
if (n < 0)
|
||
return n;
|
||
break;
|
||
|
||
case FPCI_CLASS_BRIDGE_CARDBUS:
|
||
/*
|
||
* just do a minimal setup of the bridge,
|
||
* let the OS take care of the rest
|
||
*/
|
||
FPcieAutoSetupDevice(instance_p, bdf, 0, pci_mem, pci_prefetch, pci_io,
|
||
enum_only);
|
||
|
||
printf("PCI Autoconfig: Found P2CardBus bridge, device %d\n", FPCIE_DEV(bdf));
|
||
|
||
break;
|
||
|
||
case FPCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
|
||
printf("PCI AutoConfig: Found PowerPC device\n");
|
||
/* fall through */
|
||
|
||
default:
|
||
FPcieAutoSetupDevice(instance_p, bdf, 6, pci_mem, pci_prefetch, pci_io,
|
||
enum_only);
|
||
break;
|
||
}
|
||
|
||
return FT_SUCCESS;
|
||
}
|
||
|
||
|
||
FError FPcieBindBusDevices(FPcie *instance_p, u32 bus_num, u32 parent_bdf, struct FPcieBus *bus)
|
||
{
|
||
int dev_count = 0;
|
||
u16 vendor, device;
|
||
u8 header_type;
|
||
s32 bdf, end;
|
||
bool found_multi;
|
||
FError ret;
|
||
u8 class_show;
|
||
u32 dev_exp_cap, bus_exp_cap, dev_ext_ari_cap;
|
||
u32 data;
|
||
char buf_bdf_print[20];
|
||
found_multi = false;
|
||
end = FPCIE_BDF(bus_num, FT_PCIE_CFG_MAX_NUM_OF_DEV - 1,
|
||
FT_PCIE_CFG_MAX_NUM_OF_FUN - 1);
|
||
for (bdf = FPCIE_BDF(bus_num, 0, 0); bdf <= end; //使用bus的seq成员来进行扫描，其实相当于secondory_bus号
|
||
bdf += FPCIE_BDF(0, 0, 1))
|
||
{
|
||
u32 class;
|
||
|
||
/* phytium old pci ip version, need skip in some bus */
|
||
if (instance_p->config.need_skip)
|
||
{
|
||
if (FPcieSkipDevice(instance_p->config.ecam, parent_bdf) == FPCIE_NEED_SKIP)
|
||
{
|
||
continue;
|
||
}
|
||
}
|
||
|
||
if (!FPCIE_FUNC(bdf))
|
||
found_multi = false;
|
||
if (FPCIE_FUNC(bdf) && !found_multi)
|
||
continue;
|
||
|
||
/* Check only the first access, we don't expect problems */
|
||
FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_VENDOR_REG, &vendor) ;
|
||
|
||
if (vendor == 0xffff || vendor == 0x0000)
|
||
continue;
|
||
|
||
FPcieEcamReadConfig8bit(instance_p->config.ecam, bdf, FPCIE_HEADER_TYPE_REG, &header_type) ;
|
||
|
||
if (!FPCIE_FUNC(bdf))
|
||
found_multi = header_type & 0x80;
|
||
|
||
FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_DEVICE_ID_REG, &device) ; //读取deviceid
|
||
FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, FPCI_CLASS_REVISION, &class) ; //读取classcode
|
||
class >>= 8;
|
||
|
||
FPcieEcamReadConfig8bit(instance_p->config.ecam, bdf, FPCIE_CLASS_CODE_REG, &class_show) ;
|
||
|
||
if (parent_bdf == 0xffffffff)
|
||
{
|
||
strcpy(buf_bdf_print, "root-controller");
|
||
}
|
||
else
|
||
{
|
||
sprintf(buf_bdf_print, "pci_%x:%x:%x",
|
||
FPCIE_BUS(parent_bdf), FPCIE_DEV(parent_bdf), FPCIE_FUNC(parent_bdf));
|
||
}
|
||
printf(" %02x:%02x.%02x - %04lx:%04lx %s",
|
||
FPCIE_BUS(bdf), FPCIE_DEV(bdf), FPCIE_FUNC(bdf), vendor, device,
|
||
buf_bdf_print);
|
||
printf(" 0x%.2x (%s)\n", (int)class_show, FPcieClassStr(class_show));
|
||
|
||
/* ARI function handle */
|
||
/* step 1: detect if PCI Express Device */
|
||
ret = FPcieFindCapability(instance_p, bdf, PCIE_CAP, FPCI_CAP_ID_EXP, &dev_exp_cap);
|
||
if (ret == 0 && dev_exp_cap > 0)
|
||
{
|
||
/* step2: check if the device is an ARI device */
|
||
ret = FPcieFindCapability(instance_p, bdf, PCIE_ECAP, FPCI_EXT_CAP_ID_ARI, &dev_ext_ari_cap);
|
||
if (ret == 0 && dev_ext_ari_cap > 0)
|
||
{
|
||
/* step3: check if its parent supports ARI forwarding */
|
||
ret = FPcieFindCapability(instance_p, parent_bdf, PCIE_CAP, FPCI_CAP_ID_EXP, &bus_exp_cap);
|
||
/* config bus ARI forwarding */
|
||
if (ret == 0 && bus_exp_cap > 0)
|
||
{
|
||
FPcieEcamReadConfig32bit(instance_p->config.ecam, parent_bdf,
|
||
bus_exp_cap + FPCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET, &data);
|
||
if ((data & FPCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) != 0)
|
||
{
|
||
/* step4: ARI forwarding support in bridge, so enable it */
|
||
FPcieEcamReadConfig32bit(instance_p->config.ecam, parent_bdf,
|
||
bus_exp_cap + FPCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, &data);
|
||
if (data & FPCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING == 0)
|
||
{
|
||
data |= FPCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING;
|
||
FPcieEcamWriteConfig32bit(instance_p->config.ecam, parent_bdf,
|
||
bus_exp_cap + FPCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, data);
|
||
}
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
bus->ChildN[dev_count] = bdf;
|
||
dev_count++;
|
||
|
||
//这里可以将当前的device，保存到全局变量中，供别的驱动来查询。
|
||
instance_p->scaned_bdf_array[instance_p->scaned_bdf_count] = bdf;
|
||
(instance_p->scaned_bdf_count)++;
|
||
|
||
}
|
||
bus->ChildCount = dev_count;
|
||
|
||
return FT_SUCCESS;
|
||
|
||
}
|
||
|
||
FError FPcieScanBus(FPcie *instance_p, u32 bus_num, u32 parent_bdf)
|
||
{
|
||
int i = 0;
|
||
s32 bdf;
|
||
struct FPcieBus bus;
|
||
bus.ChildCount = 0;
|
||
|
||
/* scan bus 0 device */
|
||
FPcieBindBusDevices(instance_p, bus_num, parent_bdf, &bus);
|
||
|
||
if (bus.ChildCount > 0)
|
||
{
|
||
for (i = 0; i < bus.ChildCount; i++)
|
||
{
|
||
bdf = bus.ChildN[i];
|
||
FPcieAutoConfigDevice(instance_p, bdf);
|
||
}
|
||
}
|
||
instance_p->is_scaned = 1; //表示已经扫描完成
|
||
}
|
||
|