148 lines
5.3 KiB
C
148 lines
5.3 KiB
C
////////////////////////////////////////////////////////////////////////////////
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/// @file hal_fsmc.h
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/// @author AE TEAM
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/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SDIO
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/// FIRMWARE LIBRARY.
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#ifndef __HAL_FSMC_H
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#define __HAL_FSMC_H
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// Files includes
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#include "types.h"
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#include "reg_common.h"
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#include "reg_fsmc.h"
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////////////////////////////////////////////////////////////////////////////////
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/// @addtogroup MM32_Hardware_Abstract_Layer
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup FSMC_HAL
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/// @brief FSMC HAL modules
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup FSMC_Exported_Types
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FSMC_interrupts_define
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////////////////////////////////////////////////////////////////////////////////
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// Timing parameter configuration register set selection register set0 register set1 register set2
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#define FSMC_TimingRegSelect_0 ((u32)0x00000000)
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#define FSMC_TimingRegSelect_1 ((u32)0x00000100)
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#define FSMC_TimingRegSelect_2 ((u32)0x00000200)
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// Capacity of external device
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#define FSMC_MemSize_None ((u32)0x00000000)
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#define FSMC_MemSize_64KB ((u32)0x00000001)
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#define FSMC_MemSize_128KB ((u32)0x00000002)
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#define FSMC_MemSize_256KB ((u32)0x00000002)
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#define FSMC_MemSize_512KB ((u32)0x00000004)
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#define FSMC_MemSize_1MB ((u32)0x00000005)
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#define FSMC_MemSize_2MB ((u32)0x00000006)
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#define FSMC_MemSize_4MB ((u32)0x00000007)
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#define FSMC_MemSize_8MB ((u32)0x00000008)
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#define FSMC_MemSize_16MB ((u32)0x00000009)
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#define FSMC_MemSize_32MB ((u32)0x0000000A)
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#define FSMC_MemSize_64MB ((u32)0x0000000B)
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#define FSMC_MemSize_128MB ((u32)0x0000000C)
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#define FSMC_MemSize_256MB ((u32)0x0000000D)
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#define FSMC_MemSize_512MB ((u32)0x0000000E)
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#define FSMC_MemSize_1GB ((u32)0x0000000F)
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#define FSMC_MemSize_2GB ((u32)0x00000010)
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#define FSMC_MemSize_4GB ((u32)0x00000011)
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// Memory data bus bit width setting
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typedef enum {
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FSMC_DataWidth_16bits = (0x0000), //16bits
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FSMC_DataWidth_32bits = (0x0001), //32bits
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FSMC_DataWidth_64bits = (0x0002), //64bits
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FSMC_DataWidth_128bits = (0x0003), //128bits
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FSMC_DataWidth_8bits = (0x0004), //8bits
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} FSMC_NORSRAM_DataWidth_TypeDef;
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typedef enum {
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FSMC_NORSRAM_BANK0 = 0,
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FSMC_NORSRAM_BANK1 = 1,
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FSMC_NORSRAM_BANK2 = 2,
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} FSMC_NORSRAM_BANK_TypeDef;
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typedef struct {
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u32 FSMC_SMReadPipe; //sm_read_pipe[1:0] The cycle of latching read data, that is, the cycle when ready_resp is pulled high
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u32 FSMC_ReadyMode; //Select whether the hready_resp signal comes from the FSMC IP internal or external DEVICE, only for writing and reading external DEVICE operations.
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//0: Internal FSMC 1: External DEVICE (ie from FSMC_NWAIT)
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u32 FSMC_WritePeriod; //Write cycle
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u32 FSMC_WriteHoldTime; //Address/data hold time during write operation
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u32 FSMC_AddrSetTime; //Address establishment time
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u32 FSMC_ReadPeriod; //Read cycle
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FSMC_NORSRAM_DataWidth_TypeDef FSMC_DataWidth;
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} FSMC_NORSRAM_Bank_InitTypeDef;
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typedef struct {
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u32 FSMC_Mode;
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u32 FSMC_TimingRegSelect;
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u32 FSMC_MemSize;
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u32 FSMC_MemType;
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u32 FSMC_AddrDataMode;
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} FSMC_InitTypeDef;
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#define FSMC_MemType_SDRAM ((u32)0x0<<5)
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#define FSMC_MemType_NorSRAM ((u32)0x1<<5)
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#define FSMC_MemType_FLASH ((u32)0x2<<5)
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#define FSMC_MemType_RESERVED ((u32)0x3<<5)
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//SYSCFG_CFGR1
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#define FSMC_Mode_6800 ((u32)0x40000000)
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#define FSMC_Mode_8080 ((u32)0x20000000)
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#define FSMC_Mode_NorFlash ((u32)0x00000000)
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#define FSMC_AddrDataMUX ((u32)0x00000000)
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#define FSMC_AddrDataDeMUX ((u32)0x10000000)
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void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct);
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void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct);
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void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct);
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void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank);
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/// @}
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/// @}
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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#endif // __HAL_FSMC_H
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////////////////////////////////////////////////////////////////////////////////
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