88 lines
2.7 KiB
Plaintext
88 lines
2.7 KiB
Plaintext
/*
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* Copyright 2018 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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_load_dcdc_trim()
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{
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__var ocotp_base;
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__var ocotp_fuse_bank0_base;
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__var dcdc_base;
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__var reg;
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__var trim_value;
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__var dcdc_trim_loaded;
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__var index;
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ocotp_base = 0x401F4000;
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ocotp_fuse_bank0_base = 0x401F4000 + 0x400;
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dcdc_base = 0x40080000;
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dcdc_trim_loaded = 0;
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reg = __readMemory32(ocotp_fuse_bank0_base + 0x90, "Memory");
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if (reg & (1<<10))
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{
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// DCDC: REG0->VBG_TRM
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trim_value = (reg & (0x1F << 11)) >> 11;
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reg = (__readMemory32(dcdc_base + 0x4, "Memory") & ~(0x1F << 24)) | (trim_value << 24);
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__writeMemory32(reg, dcdc_base + 0x4, "Memory");
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dcdc_trim_loaded = 1;
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}
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reg = __readMemory32(ocotp_fuse_bank0_base + 0x80, "Memory");
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if (reg & (1<<30))
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{
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index = (reg & (3 << 28)) >> 28;
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if (index < 4)
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{
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// DCDC: REG3->TRG
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reg = (__readMemory32(dcdc_base + 0xC, "Memory") & ~(0x1F)) | (0xF + index);
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__writeMemory32(reg, dcdc_base + 0xC, "Memory");
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dcdc_trim_loaded = 1;
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}
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}
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if (dcdc_trim_loaded)
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{
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// delay 1ms for dcdc to get stable
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__delay(1);
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__message "DCDC trim value loaded.\n";
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}
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}
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execUserPreload()
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{
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_load_dcdc_trim();
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}
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execUserReset()
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{
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_load_dcdc_trim();
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}
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