f0dadcb3c3
* [rv64/bsp] porting to mm * [mm] report more info for debugging * [fix] code format * [libcpu/c906] porting to RTOS * [fix] using rtdbg api * [fix] add return * [fix] report more information for debugging * [fix] use assert 0 for unrecoverable error
63 lines
1.2 KiB
ArmAsm
63 lines
1.2 KiB
ArmAsm
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/28 Bernard The unify RISC-V porting implementation
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* 2018/12/27 Jesven Add SMP support
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* 2021/02/02 lizhirui Add userspace support
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*/
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#include "cpuport.h"
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#include "stackframe.h"
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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LOAD sp, (a0)
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la s0, rt_current_thread
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LOAD s1, (s0)
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#ifdef RT_USING_SMART
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mv a0, s1
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jal lwp_aspace_switch
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#endif
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RESTORE_ALL
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sret
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/*
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* void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
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*
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* a0 --> from
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* a1 --> to
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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mv t2, sp
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li t0, 0x120//set SPIE and SPP = 1
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csrs sstatus, t0//if enter here,caller must be in system thread
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csrw sepc, ra//return address
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//saved from thread context
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SAVE_ALL
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STORE t2, 32 * REGBYTES(sp)//save user_sp
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STORE sp, (a0)
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//restore to thread context
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LOAD sp, (a1)
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la s0, rt_current_thread
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LOAD s1, (s0)
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#ifdef RT_USING_SMART
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mv a0, s1
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jal lwp_aspace_switch
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#endif
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RESTORE_ALL
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sret
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