139 lines
4.4 KiB
C
139 lines
4.4 KiB
C
/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-05-16 shelton first version
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*/
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#include "drv_adc.h"
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#include "fsl_lpadc.h"
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#include "fsl_spc.h"
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#include "fsl_common.h"
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#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)
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#define DEFAULT_HW_AVG (kLPADC_HardwareAverageCount4)
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#define DEFAULT_SAMPLE_TIME (kLPADC_SampleTimeADCK7)
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/* by default: cmd = chl+1 */
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static uint8_t adc_chl2cmd[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
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static uint8_t adc_cmd2trig[] = {0, 1, 2 ,3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3};
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struct mcx_adc
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{
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struct rt_adc_device mcx_adc_device;
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ADC_Type *adc_base;
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clock_attach_id_t clock_attach_id;
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clock_div_name_t clock_div_name;
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uint8_t clock_div;
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uint8_t referenceVoltageSource; /* 00, VREFH reference pin, 01, ANA_7(VREFI/VREFO) pin, 10, VDDA supply pin */
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char *name;
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};
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static struct mcx_adc mcx_adc_obj[] =
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{
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#ifdef BSP_USING_ADC0
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{
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.adc_base = ADC0,
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.clock_attach_id = kCLK_IN_to_ADC0,
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.clock_div_name = kCLOCK_DivAdc0Clk,
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.clock_div = 2,
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.referenceVoltageSource = 0,
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.name = "adc0",
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},
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#endif
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};
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static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled)
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{
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struct mcx_adc *adc = (struct mcx_adc *)device->parent.user_data;
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lpadc_conv_command_config_t cmd_cfg;
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LPADC_GetDefaultConvCommandConfig(&cmd_cfg);
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cmd_cfg.channelNumber = channel;
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cmd_cfg.conversionResolutionMode = kLPADC_ConversionResolutionHigh;
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cmd_cfg.hardwareAverageMode = DEFAULT_HW_AVG;
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cmd_cfg.loopCount = 0;
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cmd_cfg.sampleTimeMode = DEFAULT_SAMPLE_TIME;
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/*
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kLPADC_SampleChannelSingleEndSideA = 0U,
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kLPADC_SampleChannelSingleEndSideB = 1U,
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kLPADC_SampleChannelDiffBothSide = 2U,
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kLPADC_SampleChannelDualSingleEndBothSide =
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*/
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cmd_cfg.sampleChannelMode = kLPADC_SampleChannelSingleEndSideA;
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LPADC_SetConvCommandConfig(adc->adc_base, adc_chl2cmd[channel], &cmd_cfg);
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lpadc_conv_trigger_config_t trig_config;
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LPADC_GetDefaultConvTriggerConfig(&trig_config);
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trig_config.targetCommandId = adc_chl2cmd[channel];
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trig_config.enableHardwareTrigger = false;
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LPADC_SetConvTriggerConfig(adc->adc_base, adc_cmd2trig[trig_config.targetCommandId], &trig_config); /* Configurate the trigger0. */
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return RT_EOK;
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}
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static rt_err_t at32_get_adc_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
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{
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struct mcx_adc *adc = (struct mcx_adc *)device->parent.user_data;
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lpadc_conv_result_t mLpadcResultConfigStruct;
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LPADC_DoSoftwareTrigger(adc->adc_base, 1<<(adc_cmd2trig[adc_chl2cmd[channel]])); /* 1U is trigger0 mask. */
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while (!LPADC_GetConvResult(adc->adc_base, &mLpadcResultConfigStruct, 0))
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{
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}
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*value = mLpadcResultConfigStruct.convValue;
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return RT_EOK;
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}
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static const struct rt_adc_ops mcx_adc_ops =
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{
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.enabled = at32_adc_enabled,
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.convert = at32_get_adc_value,
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};
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static int rt_hw_adc_init(void)
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{
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int result = RT_EOK;
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int i = 0;
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/* Enable VREF */
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SPC0->ACTIVE_CFG1 |= 0xFFFFFFFF;
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SPC_SetActiveModeBandgapModeConfig(SPC0, kSPC_BandgapEnabledBufferEnabled);
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for (i = 0; i < sizeof(mcx_adc_obj) / sizeof(mcx_adc_obj[0]); i++)
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{
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CLOCK_SetClkDiv(mcx_adc_obj[i].clock_div_name, mcx_adc_obj[i].clock_div);
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CLOCK_AttachClk(mcx_adc_obj[i].clock_attach_id);
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lpadc_config_t adc_config;
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LPADC_GetDefaultConfig(&adc_config);
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adc_config.enableAnalogPreliminary = true;
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adc_config.referenceVoltageSource = mcx_adc_obj[i].referenceVoltageSource;
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adc_config.conversionAverageMode = kLPADC_ConversionAverage128; /* this is for calibartion avg mode */
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adc_config.powerLevelMode = kLPADC_PowerLevelAlt4;
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adc_config.enableConvPause = false;
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adc_config.convPauseDelay = 0;
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LPADC_Init(mcx_adc_obj[i].adc_base, &adc_config);
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LPADC_DoOffsetCalibration(mcx_adc_obj[i].adc_base);
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LPADC_DoAutoCalibration(mcx_adc_obj[i].adc_base);
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rt_hw_adc_register(&mcx_adc_obj[i].mcx_adc_device, mcx_adc_obj[i].name, &mcx_adc_ops, &mcx_adc_obj[i]);
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}
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_adc_init);
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#endif /* BSP_USING_ADC */
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