305 lines
8.1 KiB
C
305 lines
8.1 KiB
C
/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-12-1 Wayne First version
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*
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******************************************************************************/
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#include <rtconfig.h>
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#if defined(BSP_USING_PWM)
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#define LOG_TAG "drv.pwm"
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#define DBG_ENABLE
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#define DBG_SECTION_NAME "drv.pwm"
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#define DBG_LEVEL DBG_INFO
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#define DBG_COLOR
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#include <rtdbg.h>
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#include <stdint.h>
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#include <rtdevice.h>
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#include <rthw.h>
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#include "NuMicro.h"
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#include "drv_sys.h"
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enum
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{
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PWM_START = -1,
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#if defined(BSP_USING_PWM0)
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PWM0_IDX,
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#endif
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#if defined(BSP_USING_PWM1)
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PWM1_IDX,
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#endif
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PWM_CNT
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};
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#define NU_PWM_BA_DISTANCE (PWM1_BA - PWM0_BA)
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#define NU_PWM_CHANNEL_NUM 4
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struct nu_pwm
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{
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struct rt_device_pwm dev;
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char *name;
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uint32_t base_addr;
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E_SYS_IPRST rstidx;
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E_SYS_IPCLK clkidx;
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};
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typedef struct nu_pwm *nu_pwm_t;
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static struct nu_pwm nu_pwm_arr [] =
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{
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#if defined(BSP_USING_PWM0)
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{
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.name = "pwm0",
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.base_addr = PWM0_BA,
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.rstidx = PWM0RST,
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.clkidx = PWM0CKEN,
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},
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#endif
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#if defined(BSP_USING_PWM1)
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{
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.name = "pwm1",
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.base_addr = PWM1_BA,
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.rstidx = PWM1RST,
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.clkidx = PWM1CKEN,
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},
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#endif
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}; /* pwm nu_pwm */
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static rt_err_t nu_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
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static struct rt_pwm_ops nu_pwm_ops =
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{
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.control = nu_pwm_control
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};
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static rt_err_t nu_pwm_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *config, rt_bool_t enable)
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{
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nu_pwm_t psNuPWM = (nu_pwm_t)device;
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rt_err_t result = RT_EOK;
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rt_uint32_t ch = config->channel;
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if (enable == RT_TRUE)
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{
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uint32_t u32RegAdrrPCR = psNuPWM->base_addr + 0x8;
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uint32_t u32PCRChAlign = (!ch) ? 0x9 : (0x9 << (4 + ch * 4));
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/* Period and enable channel. */
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outpw(u32RegAdrrPCR, inpw(u32RegAdrrPCR) | u32PCRChAlign);
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}
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else
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{
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uint32_t u32RegAdrrPCR = psNuPWM->base_addr + 0x8;
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uint32_t u32PCRChAlign = (!ch) ? 0x1 : (0x1 << (4 + ch * 4));
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outpw(u32RegAdrrPCR, inpw(u32RegAdrrPCR) & ~u32PCRChAlign);
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}
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return result;
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}
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static rt_err_t nu_pwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *config)
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{
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nu_pwm_t psNuPWM = (nu_pwm_t)device;
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uint32_t u32RegAdrrPPR = psNuPWM->base_addr;
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uint32_t u32RegAdrrCSR = psNuPWM->base_addr + 0x04;
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uint32_t u32RegAdrrCNR = psNuPWM->base_addr + 0xC + (config->channel * 0xC);
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uint32_t u32RegAdrrCMR = psNuPWM->base_addr + 0x10 + (config->channel * 0xC);
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uint32_t u32PWMSrcClk = sysGetClock(SYS_PCLK2) * 1000000;
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uint32_t u32CMR, u32CNR;
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double douDutyCycle; /* unit:% */
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uint32_t u32PWMOutClk; /* unit:Hz */
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uint32_t u32Prescale, u32Divider;
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u32CNR = inpw(u32RegAdrrCNR) + 1;
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u32CMR = inpw(u32RegAdrrCMR) + 1;
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u32Prescale = ((inpw(u32RegAdrrPPR) & (0xff << ((config->channel >> 1) * 8))) >> ((config->channel >> 1) * 8)) + 1;
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u32Divider = (inpw(u32RegAdrrCSR) & (0x7 << (4 * config->channel))) >> (4 * config->channel);
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/* Re-convert register to real value */
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if (u32Divider == 4)
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u32Divider = 1;
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else if (u32Divider == 0)
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u32Divider = 2;
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else if (u32Divider == 1)
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u32Divider = 4;
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else if (u32Divider == 2)
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u32Divider = 8;
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else // 3
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u32Divider = 16;
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douDutyCycle = (double)u32CMR / u32CNR;
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u32PWMOutClk = u32PWMSrcClk / (u32Prescale * u32Divider * u32CNR);
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config->period = 1000000000 / u32PWMOutClk; /* In ns. */
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config->pulse = douDutyCycle * config->period;
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LOG_I("%s %d %d %d\n", ((nu_pwm_t)device)->name, config->channel, config->period, config->pulse);
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return RT_EOK;
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}
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uint32_t nu_pwm_config(uint32_t u32PwmBaseAddr, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32PulseInHz)
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{
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uint32_t i;
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uint8_t u8Divider = 1, u8Prescale = 0xFF;
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uint16_t u16CNR = 0xFFFF;
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uint16_t u16CMR = 0xFFFF;
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uint32_t u32RegAdrrPPR = u32PwmBaseAddr;
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uint32_t u32RegAdrrCSR = u32PwmBaseAddr + 0x04;
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uint32_t u32RegAdrrCNR = u32PwmBaseAddr + 0xC + (u32ChannelNum * 0xC);
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uint32_t u32RegAdrrCMR = u32PwmBaseAddr + 0x10 + (u32ChannelNum * 0xC);
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uint32_t u32PWMSrcClk = sysGetClock(SYS_PCLK2) * 1000000;
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uint32_t u32PWMOutClk = 0;
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if (u32Frequency > u32PWMSrcClk)
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return 0;
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/*
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PWM_Freq = PCLK2 / (Prescale+1) / (Clock Divider) / (CNR+1)
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PCLK / PWM_Freq = (Prescale+1) * (Clock Divider) * (CNR+1)
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PCLK / PWM_Freq / (Clock Divider) = (Prescale+1) * (CNR+1)
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*/
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/* clk divider could only be 1, 2, 4, 8, 16 */
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for (; u8Divider < 17; u8Divider <<= 1)
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{
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i = (u32PWMSrcClk / u32Frequency) / u8Divider;
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/* If target value is larger than CNR * prescale, need to use a larger divider */
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if (i > (0x10000 * 0x100))
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continue;
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/* CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF */
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u8Prescale = (i + 0xFFFF) / 0x10000;
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/* u8Prescale must at least be 2, otherwise the output stop */
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if (u8Prescale < 2)
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u8Prescale = 2;
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i /= u8Prescale;
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if (i < 0x10000)
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{
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if (i == 1)
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u16CNR = 1; // Too fast, and PWM cannot generate expected frequency...
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else
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u16CNR = i;
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break;
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}
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}
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u32PWMOutClk = u32PWMSrcClk / (u8Prescale * u8Divider * u16CNR);
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/* For fill into registers. */
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u8Prescale -= 1;
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u16CNR -= 1;
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/* Convert to real register value */
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if (u8Divider == 1)
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u8Divider = 4;
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else if (u8Divider == 2)
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u8Divider = 0;
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else if (u8Divider == 4)
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u8Divider = 1;
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else if (u8Divider == 8)
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u8Divider = 2;
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else // 16
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u8Divider = 3;
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/* Every two channels share a prescaler */
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outpw(u32RegAdrrPPR, (inpw(u32RegAdrrPPR) & ~(0xff << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8)));
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/* Update CLKSEL in specified channel in CSR field. */
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outpw(u32RegAdrrCSR, inpw(u32RegAdrrCSR) & ~(0x7 << (4 * u32ChannelNum)) | (u8Divider << (4 * u32ChannelNum)));
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u16CMR = u32Frequency * (u16CNR + 1) / u32PulseInHz;
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outpw(u32RegAdrrCMR, (u16CMR == 0) ? 0 : u16CMR - 1);
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outpw(u32RegAdrrCNR, u16CNR);
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return (u32PWMOutClk);
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}
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static rt_err_t nu_pwm_set(struct rt_device_pwm *device, struct rt_pwm_configuration *config)
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{
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nu_pwm_t psNuPWM = (nu_pwm_t)device;
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rt_err_t result = RT_EINVAL;
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rt_uint32_t u32FreqInHz; /* unit:Hz */
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rt_uint32_t u32PulseInHz; /* unit:% */
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if (config->period < 1000 || !config->period || !config->pulse)
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goto exit_nu_pwm_set;
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/* Calculate frequency, Unit is in us. */
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u32FreqInHz = (1000000000) / config->period;
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u32PulseInHz = (1000000000) / config->pulse;
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nu_pwm_config(psNuPWM->base_addr, config->channel, u32FreqInHz, u32PulseInHz);
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result = RT_EOK;
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exit_nu_pwm_set:
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return -(result);
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}
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static rt_err_t nu_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *config = (struct rt_pwm_configuration *)arg;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(config != RT_NULL);
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if (config->channel > NU_PWM_CHANNEL_NUM)
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return -(RT_EINVAL);
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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return nu_pwm_enable(device, config, RT_TRUE);
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case PWM_CMD_DISABLE:
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return nu_pwm_enable(device, config, RT_FALSE);
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case PWM_CMD_SET:
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return nu_pwm_set(device, config);
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case PWM_CMD_GET:
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return nu_pwm_get(device, config);
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default:
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break;
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}
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return -(RT_ERROR);
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}
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int rt_hw_pwm_init(void)
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{
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rt_err_t ret;
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int i;
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for (i = (PWM_START + 1); i < PWM_CNT; i++)
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{
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nu_sys_ipclk_enable(nu_pwm_arr[i].clkidx);
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nu_sys_ip_reset(nu_pwm_arr[i].rstidx);
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ret = rt_device_pwm_register(&nu_pwm_arr[i].dev, nu_pwm_arr[i].name, &nu_pwm_ops, RT_NULL);
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RT_ASSERT(ret == RT_EOK);
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}
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return 0;
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}
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INIT_DEVICE_EXPORT(rt_hw_pwm_init);
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#endif
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