74 lines
1.9 KiB
C
74 lines
1.9 KiB
C
/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-11-11 Wayne First version
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*
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******************************************************************************/
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#include <rtthread.h>
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#include <rthw.h>
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#include "board.h"
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#include "drv_uart.h"
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#include "drv_sys.h"
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#if defined(BSP_USING_MMU)
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static struct mem_desc hw_mem_desc[] =
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{
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{ 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */
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{ 0x00000000, BOARD_SDRAM_SIZE - 1, 0x00000000, RW_CB }, /* 64M cached DDR memory */
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{ BIT31, (BIT31 | BOARD_SDRAM_SIZE) - 1, BIT31, RW_NCNB }, /* Shadow DDR Map */
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{ 0x3C000000, 0x3C004000 - 1, 0x3C000000, RW_NCNB }, /* 16K SRAM memory */
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{ 0xBC000000, 0xBC004000 - 1, 0xBC000000, RW_NCNB } /* 16K Shadow memory */
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};
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#endif
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/**
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* This function will initial M487 board.
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*/
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RT_WEAK void rt_hw_board_init(void)
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{
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/* initialize base clock */
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nu_clock_base_init();
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/* initialize peripheral pin function */
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nu_pin_init();
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#if defined(BSP_USING_MMU)
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/* initialize mmu */
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rt_hw_mmu_init(&hw_mem_desc[0], sizeof(hw_mem_desc) / sizeof(hw_mem_desc[0]));
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#else
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/* disable I/D cache */
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mmu_disable_dcache();
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mmu_disable_icache();
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mmu_disable();
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mmu_invalidate_tlb();
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#endif
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/* initialize hardware interrupt */
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rt_hw_interrupt_init();
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/* initialize systick */
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rt_hw_systick_init();
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#ifdef RT_USING_HEAP
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/* init memory system */
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rt_system_heap_init((void *)BOARD_HEAP_START, (void *)BOARD_HEAP_END);
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#endif
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/* initialize uart */
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rt_hw_uart_init();
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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}
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