302 lines
11 KiB
C
302 lines
11 KiB
C
/*
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******************************************************************************
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* @file HAL_SPI.h
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* @version V1.0.0
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* @date 2020
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* @brief Header file of SPI HAL module.
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******************************************************************************
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*/
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#ifndef __HAL_SPI_H__
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#define __HAL_SPI_H__
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#include "ACM32Fxx_HAL.h"
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/**************** Bit definition for SPI_CTL register **************************/
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#define SPI_CTL_CS_TIME (BIT11|BIT12|BIT13|BIT14|BIT15|BIT16|BIT17|BIT18)
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#define SPI_CTL_CS_FILTER BIT10
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#define SPI_CTL_CS_RST BIT9
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#define SPI_CTL_SLAVE_EN BIT8
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#define SPI_CTL_IO_MODE BIT7
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#define SPI_CTL_X_MODE (BIT6|BIT5)
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#define SPI_CTL_LSB_FIRST BIT4
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#define SPI_CTL_CPOL BIT3
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#define SPI_CTL_CPHA BIT2
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#define SPI_CTL_SFILTER BIT1
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#define SPI_CTL_MST_MODE BIT0
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/**************** Bit definition for SPI_TX_CTL register ***********************/
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#define SPI_TX_CTL_DMA_LEVEL (BIT4|BIT5|BIT6|BIT7)
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#define SPI_TX_CTL_DMA_LEVEL_3 BIT7
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#define SPI_TX_CTL_DMA_LEVEL_2 BIT6
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#define SPI_TX_CTL_DMA_LEVEL_1 BIT5
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#define SPI_TX_CTL_DMA_LEVEL_0 BIT4
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#define SPI_TX_CTL_DMA_REQ_EN BIT3
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#define SPI_TX_CTL_MODE BIT2
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#define SPI_TX_CTL_FIFO_RESET BIT1
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#define SPI_TX_CTL_EN BIT0
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/**************** Bit definition for SPI_RX_CTL register ***********************/
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#define SPI_RX_CTL_DMA_LEVEL (BIT4|BIT5|BIT6|BIT7)
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#define SPI_RX_CTL_DMA_LEVEL_3 BIT7
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#define SPI_RX_CTL_DMA_LEVEL_2 BIT6
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#define SPI_RX_CTL_DMA_LEVEL_1 BIT5
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#define SPI_RX_CTL_DMA_LEVEL_0 BIT4
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#define SPI_RX_CTL_DMA_REQ_EN BIT3
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#define SPI_RX_CTL_FIFO_RESET BIT1
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#define SPI_RX_CTL_EN BIT0
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/**************** Bit definition for SPI_IE register ***************************/
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#define SPI_IE_RX_BATCH_DONE_EN BIT15
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#define SPI_IE_TX_BATCH_DONE_EN BIT14
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#define SPI_IE_RX_FIFO_FULL_OV_EN BIT13
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#define SPI_IE_RX_FIFO_EMPTY_OV_EN BIT12
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#define SPI_IE_RX_NOT_EMPTY_EN BIT11
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#define SPI_IE_CS_POS_EN BIT10
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#define SPI_IE_RX_FIFO_HALF_FULL_EN BIT9
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#define SPI_IE_RX_FIFO_HALF_EMPTY_EN BIT8
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#define SPI_IE_TX_FIFO_HALF_FULL_EN BIT7
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#define SPI_IE_TX_FIFO_HALF_EMPTY_EN BIT6
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#define SPI_IE_RX_FIFO_FULL_EN BIT5
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#define SPI_IE_RX_FIFO_EMPTY_EN BIT4
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#define SPI_IE_TX_FIFO_FULL_EN BIT3
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#define SPI_IE_TX_FIFO_EMPTY_EN BIT2
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#define SPI_IE_BATCH_DONE_EN BIT1
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/**************** Bit definition for SPI_STATUS register ***********************/
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#define SPI_STATUS_RX_BATCH_DONE BIT15
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#define SPI_STATUS_TX_BATCH_DONE BIT14
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#define SPI_STATUS_RX_FIFO_FULL_OV BIT13
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#define SPI_STATUS_RX_FIFO_EMPTY_OV BIT12
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#define SPI_STATUS_RX_NOT_EMPTY BIT11
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#define SPI_STATUS_CS_POS BIT10
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#define SPI_STATUS_RX_FIFO_HALF_FULL BIT9
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#define SPI_STATUS_RX_FIFO_HALF_EMPTY BIT8
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#define SPI_STATUS_TX_FIFO_HALF_FULL BIT7
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#define SPI_STATUS_TX_FIFO_HALF_EMPTY BIT6
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#define SPI_STATUS_RX_FIFO_FULL BIT5
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#define SPI_STATUS_RX_FIFO_EMPTY BIT4
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#define SPI_STATUS_TX_FIFO_FULL BIT3
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#define SPI_STATUS_TX_FIFO_EMPTY BIT2
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#define SPI_STATUS_BATCH_DONE BIT1
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#define SPI_STATUS_TX_BUSY BIT0
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/**************** Bit definition for SPI_CS register ***************************/
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#define SPI_CS_CSX BIT1
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#define SPI_CS_CS0 BIT0
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/**************** Bit definition for SPI_OUT_EN register ***********************/
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#define SPI_HOLD_EN BIT3
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#define SPI_HOLD_WP_EN BIT2
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#define SPI_HOLD_MISO_EN BIT1
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#define SPI_HOLD_MOSI_EN BIT0
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/**************** Bit definition for SPI_MEMO_ACC register ***********************/
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#define SPI_ADDR_WIDTH (BIT14|BIT15|BIT16|BIT17|BIT18)
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#define SPI_PARA_NO2 (BIT9|BIT10|BIT11|BIT12|BIT13)
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#define SPI_PARA_NO1 (BIT5|BIT6|BIT7|BIT8)
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#define SPI_CON_RD_EN BIT3
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#define SPI_PARA_ORD2 BIT2
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#define SPI_PARA_ORD1 BIT1
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#define SPI_ACC_EN BIT0
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/** @defgroup SLAVE State machine
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* @{
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*/
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#define SPI_RX_STATE_IDLE (0U)
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#define SPI_RX_STATE_RECEIVING (1U)
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#define SPI_TX_STATE_IDLE (0U)
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#define SPI_TX_STATE_SENDING (1U)
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/**
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* @}
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*/
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/** @defgroup SPI_MODE
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* @{
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*/
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#define SPI_MODE_SLAVE (0U)
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#define SPI_MODE_MASTER (1U)
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/**
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* @}
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*/
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/** @defgroup SPI_WORK_MODE
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* @{
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*/
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#define SPI_WORK_MODE_0 (0x00000000)
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#define SPI_WORK_MODE_1 (0x00000004)
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#define SPI_WORK_MODE_2 (0x00000008)
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#define SPI_WORK_MODE_3 (0x0000000C)
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/**
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* @}
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*/
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/** @defgroup SPI_CLOCK_PHASE SPI Clock Phase
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* @{
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*/
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#define SPI_PHASE_1EDGE (0U)
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#define SPI_PHASE_2EDGE (1U)
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/**
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* @}
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*/
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/** @defgroup X_MODE SPI Clock Phase
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* @{
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*/
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#define SPI_1X_MODE (0x00000000)
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#define SPI_2X_MODE (0x00000020)
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#define SPI_4X_MODE (0x00000040)
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/**
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* @}
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*/
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/** @defgroup SPI_MSB_LSB_FIRST
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* @{
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*/
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#define SPI_FIRSTBIT_MSB (0U)
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#define SPI_FIRSTBIT_LSB (1U)
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/**
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* @}
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*/
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/** @defgroup BAUDRATE_PRESCALER
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* @{
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*/
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#define SPI_BAUDRATE_PRESCALER_4 (4U)
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#define SPI_BAUDRATE_PRESCALER_8 (8U)
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#define SPI_BAUDRATE_PRESCALER_16 (16U)
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#define SPI_BAUDRATE_PRESCALER_32 (32U)
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#define SPI_BAUDRATE_PRESCALER_64 (64U)
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#define SPI_BAUDRATE_PRESCALER_128 (128U)
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#define SPI_BAUDRATE_PRESCALER_254 (254U)
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/**
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* @}
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*/
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/**
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* @brief SPI Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t SPI_Mode; /* This parameter can be a value of @ref SPI_MODE */
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uint32_t SPI_Work_Mode; /* This parameter can be a value of @ref SPI_WORK_MODE */
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uint32_t X_Mode; /* This parameter can be a value of @ref X_MODE */
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uint32_t First_Bit; /* This parameter can be a value of @ref SPI_MSB_LSB_FIRST */
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uint32_t BaudRate_Prescaler; /* This parameter can be a value of @ref BAUDRATE_PRESCALER */
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}SPI_InitTypeDef;
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/******************************** Check SPI Parameter *******************************/
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#define IS_SPI_ALL_MODE(SPI_Mode) (((SPI_Mode) == SPI_MODE_SLAVE) || \
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((SPI_Mode) == SPI_MODE_MASTER))
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#define IS_SPI_WORK_MODE(WORK_MODE) (((WORK_MODE) == SPI_WORK_MODE_0) || \
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((WORK_MODE) == SPI_WORK_MODE_1) || \
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((WORK_MODE) == SPI_WORK_MODE_2) || \
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((WORK_MODE) == SPI_WORK_MODE_3))
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#define IS_SPI_X_MODE(X_MODE) (((X_MODE) == SPI_1X_MODE) || \
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((X_MODE) == SPI_2X_MODE) || \
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((X_MODE) == SPI_4X_MODE))
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#define IS_SPI_FIRST_BIT(FIRST_BIT) (((FIRST_BIT) == SPI_FIRSTBIT_MSB) || \
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((FIRST_BIT) == SPI_FIRSTBIT_LSB))
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#define IS_SPI_BAUDRATE_PRESCALER(BAUDRATE) (((BAUDRATE) == SPI_BAUDRATE_PRESCALER_4) || \
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((BAUDRATE) == SPI_BAUDRATE_PRESCALER_8) || \
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((BAUDRATE) == SPI_BAUDRATE_PRESCALER_16) || \
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((BAUDRATE) == SPI_BAUDRATE_PRESCALER_32) || \
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((BAUDRATE) == SPI_BAUDRATE_PRESCALER_64) || \
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((BAUDRATE) == SPI_BAUDRATE_PRESCALER_128) || \
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((BAUDRATE) == SPI_BAUDRATE_PRESCALER_254))
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/**
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* @brief SPI handle Structure definition
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*/
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typedef struct
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{
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SPI_TypeDef *Instance; /* SPI registers base address */
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SPI_InitTypeDef Init; /* SPI communication parameters */
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uint32_t RxState; /* SPI state machine */
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uint32_t TxState; /* SPI state machine */
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uint8_t *Rx_Buffer; /* SPI Rx Buffer */
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uint8_t *Tx_Buffer; /* SPI Tx Buffer */
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uint32_t Rx_Size; /* SPI Rx Size */
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uint32_t Tx_Size; /* SPI Tx Size */
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uint32_t Rx_Count; /* SPI RX Count */
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uint32_t Tx_Count; /* SPI TX Count */
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DMA_HandleTypeDef *HDMA_Rx; /* SPI Rx DMA handle parameters */
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DMA_HandleTypeDef *HDMA_Tx; /* SPI Tx DMA handle parameters */
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}SPI_HandleTypeDef;
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/******************************** SPI Instances *******************************/
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#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2) || ((INSTANCE) == SPI3) || ((INSTANCE) == SPI4))
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/* Function : HAL_SPI_IRQHandler */
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void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
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/* Function : HAL_SPI_MspInit */
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void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
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/* Function : HAL_SPI_MspDeInit */
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void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
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/* Function : HAL_SPI_Init */
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HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
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/* Function : HAL_SPI_DeInit */
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HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
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/* Function : HAL_SPI_Transmit */
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HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
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/* Function : HAL_SPI_Transmit_DMA */
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HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size);
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/* Function : HAL_SPI_Receive */
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HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
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/* Function : HAL_SPI_Receive_DMA */
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HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size);
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/* Function : HAL_SPI_Wire_Config */
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HAL_StatusTypeDef HAL_SPI_Wire_Config(SPI_HandleTypeDef *hspi, uint32_t X_Mode);
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/* Function : HAL_SPI_Transmit_IT */
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HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size);
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/* Function : HAL_SPI_Receive_IT */
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HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size);
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/* Function : HAL_SPI_TransmitReceive */
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HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint32_t Size, uint32_t Timeout);
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/* Function : HAL_SPI_GetTxState */
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uint8_t HAL_SPI_GetTxState(SPI_HandleTypeDef *hspi);
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/* Function : HAL_SPI_GetRxState */
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uint8_t HAL_SPI_GetRxState(SPI_HandleTypeDef *hspi);
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#endif
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