ecf2d82159
* Synchronize the code of the rt mart branch to the master branch.
* TTY device
* Add lwP code from rt-smart
* Add vnode in DFS, but DFS will be re-write for rt-smart
* There are three libcpu for rt-smart:
* arm/cortex-a, arm/aarch64
* riscv64
Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>
65 lines
1.0 KiB
C
65 lines
1.0 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-01-29 lizhirui first version
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*/
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#include <rthw.h>
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#include <rtdef.h>
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#include <board.h>
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#include <riscv.h>
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#include <cache.h>
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rt_inline rt_uint32_t rt_cpu_icache_line_size()
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{
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return 0;
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}
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rt_inline rt_uint32_t rt_cpu_dcache_line_size()
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{
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return 0;
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}
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void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
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{
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if (ops == RT_HW_CACHE_INVALIDATE)
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{
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rt_hw_cpu_icache_invalidate(addr, size);
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}
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}
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void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
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{
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if (ops == RT_HW_CACHE_FLUSH)
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{
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rt_hw_cpu_dcache_clean(addr, size);
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}
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else
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{
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rt_hw_cpu_dcache_invalidate(addr, size);
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}
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}
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rt_base_t rt_hw_cpu_icache_status_local()
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{
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return 0;
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}
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rt_base_t rt_hw_cpu_dcache_status()
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{
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return 0;
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}
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void rt_hw_sync_cache_local(void *addr, int size)
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{
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}
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int sys_cacheflush(void *addr, int size, int cache)
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{
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return 0;
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}
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