225 lines
7.6 KiB
C
225 lines
7.6 KiB
C
/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_flexram.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the instance from the base address to be used to gate or ungate the module clock
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*
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* @param base FLEXRAM base address
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*
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* @return The FLEXRAM instance
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*/
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static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base);
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/*!
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* @brief FLEXRAM map TCM size to register value
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*
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* @param tcmBankNum tcm banknumber
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* @retval register value correspond to the tcm size
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*/
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static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum);
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/*!
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* @brief FLEXRAM configure TCM size
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* This function is used to set the TCM to the actual size.When access to the TCM memory boundary ,hardfault will
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* raised by core.
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* @param itcmBankNum itcm bank number to allocate
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* @param dtcmBankNum dtcm bank number to allocate
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*/
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static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to FLEXRAM bases for each instance. */
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static FLEXRAM_Type *const s_flexramBases[] = FLEXRAM_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to FLEXRAM clocks for each instance. */
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static const clock_ip_name_t s_flexramClocks[] = FLEXRAM_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_flexramBases); instance++)
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{
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if (s_flexramBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_flexramBases));
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return instance;
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}
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void FLEXRAM_Init(FLEXRAM_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate ENET clock. */
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CLOCK_EnableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* enable all the interrupt status */
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base->INT_STAT_EN |= kFLEXRAM_InterruptStatusAll;
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/* clear all the interrupt status */
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base->INT_STATUS |= kFLEXRAM_InterruptStatusAll;
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/* disable all the interrpt */
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base->INT_SIG_EN = 0U;
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}
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void FLEXRAN_Deinit(FLEXRAM_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate ENET clock. */
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CLOCK_DisableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum)
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{
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uint8_t tcmSizeConfig = 0U;
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switch (tcmBankNum * FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE)
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{
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case kFLEXRAM_TCMSize32KB:
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tcmSizeConfig = 6U;
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break;
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case kFLEXRAM_TCMSize64KB:
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tcmSizeConfig = 7U;
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break;
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case kFLEXRAM_TCMSize128KB:
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tcmSizeConfig = 8U;
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break;
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case kFLEXRAM_TCMSize256KB:
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tcmSizeConfig = 9U;
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break;
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case kFLEXRAM_TCMSize512KB:
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tcmSizeConfig = 10U;
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break;
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default:
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break;
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}
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return tcmSizeConfig;
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}
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static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
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{
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/* dtcm configuration */
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if (dtcmBankNum != 0U)
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{
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IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_MASK;
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IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ(FLEXRAM_MapTcmSizeToRegister(dtcmBankNum));
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IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK;
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}
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else
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{
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IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK;
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}
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/* itcm configuration */
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if (itcmBankNum != 0U)
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{
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IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_MASK;
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IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ(FLEXRAM_MapTcmSizeToRegister(itcmBankNum));
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IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK;
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}
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else
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{
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IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK;
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}
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return kStatus_Success;
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}
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status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config)
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{
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uint8_t dtcmBankNum = config->dtcmBankNum;
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uint8_t itcmBankNum = config->itcmBankNum;
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uint8_t ocramBankNum = config->ocramBankNum;
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uint32_t bankCfg = 0U, i = 0U;
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/* check the arguments */
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if ((FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum)) ||
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((dtcmBankNum != 0U) && ((dtcmBankNum & (dtcmBankNum - 1u)) != 0U)) ||
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((itcmBankNum != 0U) && ((itcmBankNum & (itcmBankNum - 1u)) != 0U)))
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{
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return kStatus_InvalidArgument;
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}
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/* flexram bank config value */
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for (i = 0U; i < FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS; i++)
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{
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if (i < ocramBankNum)
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{
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bankCfg |= ((uint32_t)kFLEXRAM_BankOCRAM) << (i * 2);
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continue;
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}
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if (i < (dtcmBankNum + ocramBankNum))
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{
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bankCfg |= ((uint32_t)kFLEXRAM_BankDTCM) << (i * 2);
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continue;
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}
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if (i < (dtcmBankNum + ocramBankNum + itcmBankNum))
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{
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bankCfg |= ((uint32_t)kFLEXRAM_BankITCM) << (i * 2);
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continue;
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}
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}
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IOMUXC_GPR->GPR17 = bankCfg;
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/* set TCM size */
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FLEXRAM_SetTCMSize(itcmBankNum, dtcmBankNum);
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/* select ram allocate source from FLEXRAM_BANK_CFG */
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FLEXRAM_SetAllocateRamSrc(kFLEXRAM_BankAllocateThroughBankCfg);
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return kStatus_Success;
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}
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