153 lines
3.5 KiB
C
153 lines
3.5 KiB
C
/*
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-3-08 GuEe-GUI the first version
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*/
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#ifndef __ROCKCHIP_CLK_H__
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#define __ROCKCHIP_CLK_H__
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "reset/reset.h"
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#include <stdlib.h>
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#include "../rockchip.h"
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#define HZ 100
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#define KHZ 1000
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#define MHZ 1000000
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#define OSC_HZ (24 * MHZ)
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struct rk_cpu_rate_table
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{
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rt_ubase_t rate;
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rt_uint32_t aclk_div;
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rt_uint32_t pclk_div;
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};
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struct rk_pll_rate_table
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{
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rt_ubase_t rate;
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union {
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struct {
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/* for RK3066 */
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rt_uint32_t nr;
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rt_uint32_t nf;
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rt_uint32_t no;
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rt_uint32_t nb;
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};
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struct {
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/* for RK3036/RK3399 */
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rt_uint32_t fbdiv;
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rt_uint32_t postdiv1;
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rt_uint32_t refdiv;
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rt_uint32_t postdiv2;
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rt_uint32_t dsmpd;
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rt_uint32_t frac;
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};
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struct {
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/* for RK3588 */
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rt_uint32_t m;
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rt_uint32_t p;
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rt_uint32_t s;
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rt_uint32_t k;
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};
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};
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};
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enum rk_pll_type {
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pll_rk3036,
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pll_rk3066,
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pll_rk3328,
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pll_rk3366,
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pll_rk3399,
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pll_rk3588,
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};
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typedef rt_uint32_t rk_pll_type_t;
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struct rk_pll_clock
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{
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rt_uint32_t id;
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rt_uint32_t con_offset;
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rt_uint32_t mode_offset;
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rt_uint32_t mode_shift;
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rt_uint32_t lock_shift;
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rk_pll_type_t type;
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rt_uint32_t pll_flags;
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struct rk_pll_rate_table *rate_table;
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rt_uint32_t mode_mask;
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};
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struct rk_clk_gate
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{
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const char *name;
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const char *parent_name;
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int con_idx;
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int con_bit;
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};
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#define GATE(_id, _name, \
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_pname, _con_idx, _con_bit) \
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[_id] = \
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{ \
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.name = _name, \
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.parent_name = _pname, \
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.con_idx = _con_idx, \
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.con_bit = _con_bit, \
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}
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#define CPUCLK_RATE(_rate, \
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_aclk_div, _pclk_div) \
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{ \
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.rate = _rate##U, \
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.aclk_div = _aclk_div, \
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.pclk_div = _pclk_div, \
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}
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#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, \
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_postdiv1, _postdiv2, _dsmpd, _frac) \
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{ \
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.rate = _rate##U, \
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.fbdiv = _fbdiv, \
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.postdiv1 = _postdiv1, \
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.refdiv = _refdiv, \
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.postdiv2 = _postdiv2, \
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.dsmpd = _dsmpd, \
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.frac = _frac, \
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}
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#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
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{ \
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.rate = _rate##U, \
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.p = _p, \
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.m = _m, \
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.s = _s, \
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.k = _k, \
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}
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#define PLL(_type, _id, _con, _mode, _mshift, \
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_lshift, _pflags, _rtable) \
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{ \
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.type = _type, \
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.id = _id, \
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.con_offset = _con, \
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.mode_offset = _mode, \
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.mode_shift = _mshift, \
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.lock_shift = _lshift, \
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.pll_flags = _pflags, \
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.rate_table = _rtable, \
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}
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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#define ROCKCHIP_SOFTRST_HIWORD_MASK RT_BIT(0)
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#endif /* __ROCKCHIP_CLK_H__ */
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