649 lines
15 KiB
C
649 lines
15 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-03-04 stevetong459 first version
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* 2022-07-15 Aligagago add APM32F4 series MCU support
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* 2022-12-26 luobeihai add APM32F0 series MCU support
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* 2023-03-27 luobeihai add APM32E1/S1 series MCU support
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*/
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#include <board.h>
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#ifdef RT_USING_PWM
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#include <drivers/rt_drv_pwm.h>
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#define DBG_TAG "drv.pwm"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#define MAX_PERIOD 65535
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#define MIN_PERIOD 3
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#define MIN_PULSE 2
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/* Init timer gpio and enable clock */
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extern void apm32_msp_timer_init(void *Instance);
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enum
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{
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#ifdef BSP_USING_PWM1
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PWM1_INDEX,
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#endif
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#ifdef BSP_USING_PWM2
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PWM2_INDEX,
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#endif
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#ifdef BSP_USING_PWM3
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PWM3_INDEX,
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#endif
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#ifdef BSP_USING_PWM4
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PWM4_INDEX,
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#endif
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#ifdef BSP_USING_PWM5
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PWM5_INDEX,
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#endif
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#ifdef BSP_USING_PWM8
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PWM8_INDEX,
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#endif
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#ifdef BSP_USING_PWM9
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PWM9_INDEX,
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#endif
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#ifdef BSP_USING_PWM10
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PWM10_INDEX,
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#endif
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#ifdef BSP_USING_PWM11
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PWM11_INDEX,
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#endif
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#ifdef BSP_USING_PWM12
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PWM12_INDEX,
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#endif
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#ifdef BSP_USING_PWM13
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PWM13_INDEX,
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#endif
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#ifdef BSP_USING_PWM14
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PWM14_INDEX,
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#endif
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#ifdef BSP_USING_PWM15
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PWM15_INDEX,
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#endif
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#ifdef BSP_USING_PWM16
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PWM16_INDEX,
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#endif
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#ifdef BSP_USING_PWM17
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PWM17_INDEX,
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#endif
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};
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struct apm32_pwm
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{
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char *name;
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TMR_T *tmr;
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rt_uint8_t channel;
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struct rt_device_pwm pwm_device;
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};
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static struct apm32_pwm pwm_config[] =
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{
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#ifdef BSP_USING_PWM1
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{
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"pwm1",
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TMR1,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM2
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{
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"pwm2",
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TMR2,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM3
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{
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"pwm3",
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TMR3,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM4
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{
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"pwm4",
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TMR4,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM5
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{
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"pwm5",
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TMR5,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM8
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{
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"pwm8",
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TMR8,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM9
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{
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"pwm9",
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TMR9,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM10
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{
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"pwm10",
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TMR10,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM11
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{
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"pwm11",
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TMR11,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM12
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{
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"pwm12",
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TMR12,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM13
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{
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"pwm13",
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TMR13,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM14
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{
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"pwm14",
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TMR14,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM15
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{
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"pwm15",
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TMR15,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM16
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{
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"pwm16",
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TMR16,
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0,
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},
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#endif
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#ifdef BSP_USING_PWM17
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{
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"pwm17",
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TMR17,
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0,
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},
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#endif
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};
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static void pwm_channel_init(void)
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{
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#ifdef BSP_USING_PWM1_CH1
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pwm_config[PWM1_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM1_CH2
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pwm_config[PWM1_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM1_CH3
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pwm_config[PWM1_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM1_CH4
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pwm_config[PWM1_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM2_CH1
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pwm_config[PWM2_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM2_CH2
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pwm_config[PWM2_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM2_CH3
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pwm_config[PWM2_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM2_CH4
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pwm_config[PWM2_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM3_CH1
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pwm_config[PWM3_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM3_CH2
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pwm_config[PWM3_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM3_CH3
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pwm_config[PWM3_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM3_CH4
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pwm_config[PWM3_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM4_CH1
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pwm_config[PWM4_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM4_CH2
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pwm_config[PWM4_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM4_CH3
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pwm_config[PWM4_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM4_CH4
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pwm_config[PWM4_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM5_CH1
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pwm_config[PWM5_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM5_CH2
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pwm_config[PWM5_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM5_CH3
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pwm_config[PWM5_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM5_CH4
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pwm_config[PWM5_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM8_CH1
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pwm_config[PWM8_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM8_CH2
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pwm_config[PWM8_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM8_CH3
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pwm_config[PWM8_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM8_CH4
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pwm_config[PWM8_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM9_CH1
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pwm_config[PWM9_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM9_CH2
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pwm_config[PWM9_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM10_CH1
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pwm_config[PWM10_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM11_CH1
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pwm_config[PWM11_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM12_CH1
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pwm_config[PWM12_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM12_CH2
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pwm_config[PWM12_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM13_CH1
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pwm_config[PWM13_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM14_CH1
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pwm_config[PWM14_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM15_CH1
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pwm_config[PWM15_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM15_CH2
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pwm_config[PWM15_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM16_CH1
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pwm_config[PWM16_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM17_CH1
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pwm_config[PWM17_INDEX].channel |= 1 << 0;
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#endif
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}
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static rt_err_t apm32_pwm_hw_init(struct apm32_pwm *device)
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{
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rt_err_t result = RT_EOK;
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TMR_T *tmr = RT_NULL;
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RT_ASSERT(device != RT_NULL);
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tmr = (TMR_T *)device->tmr;
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/* Init timer gpio and enable clock */
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apm32_msp_timer_init(tmr);
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#if defined(SOC_SERIES_APM32F0)
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TMR_TimeBase_T base_config;
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TMR_OCConfig_T oc_config;
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/* configure the tmrer to pwm mode */
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base_config.div = 0;
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base_config.counterMode = TMR_COUNTER_MODE_UP;
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base_config.period = 0;
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base_config.clockDivision = TMR_CKD_DIV1;
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TMR_ConfigTimeBase(tmr, &base_config);
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TMR_SelectOutputTrigger(tmr, TMR_TRGOSOURCE_RESET);
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TMR_DisableMasterSlaveMode(tmr);
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oc_config.OC_Mode = TMR_OC_MODE_PWM1;
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oc_config.Pulse = 0;
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oc_config.OC_Polarity = TMR_OC_POLARITY_HIGH;
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oc_config.OC_NIdlestate = TMR_OCNIDLESTATE_RESET;
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oc_config.OC_Idlestate = TMR_OCIDLESTATE_RESET;
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oc_config.OC_OutputState = TMR_OUTPUT_STATE_ENABLE;
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/* config pwm channel */
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if (device->channel & 0x01)
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{
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TMR_OC1Config(tmr, &oc_config);
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}
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if (device->channel & 0x02)
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{
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TMR_OC2Config(tmr, &oc_config);
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}
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if (device->channel & 0x04)
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{
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TMR_OC3Config(tmr, &oc_config);
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}
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if (device->channel & 0x08)
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{
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TMR_OC4Config(tmr, &oc_config);
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}
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/* enable update request source */
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TMR_ConfigUPdateRequest(tmr, TMR_UPDATE_SOURCE_REGULAR);
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#elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1) \
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|| defined(SOC_SERIES_APM32F4)
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TMR_BaseConfig_T base_config;
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TMR_OCConfig_T oc_config;
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/* configure the tmrer to pwm mode */
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base_config.division = 0;
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base_config.countMode = TMR_COUNTER_MODE_UP;
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base_config.period = 0;
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base_config.clockDivision = TMR_CLOCK_DIV_1;
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TMR_ConfigTimeBase(tmr, &base_config);
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TMR_SelectOutputTrigger(tmr, TMR_TRGO_SOURCE_RESET);
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TMR_DisableMasterSlaveMode(tmr);
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oc_config.mode = TMR_OC_MODE_PWM1;
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oc_config.pulse = 0;
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oc_config.polarity = TMR_OC_POLARITY_HIGH;
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oc_config.nIdleState = TMR_OC_NIDLE_STATE_RESET;
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oc_config.idleState = TMR_OC_IDLE_STATE_RESET;
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oc_config.outputState = TMR_OC_STATE_ENABLE;
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/* config pwm channel */
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if (device->channel & 0x01)
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{
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TMR_ConfigOC1(tmr, &oc_config);
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}
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if (device->channel & 0x02)
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{
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TMR_ConfigOC2(tmr, &oc_config);
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}
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if (device->channel & 0x04)
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{
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TMR_ConfigOC3(tmr, &oc_config);
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}
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if (device->channel & 0x08)
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{
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TMR_ConfigOC4(tmr, &oc_config);
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}
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/* enable update request source */
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#if defined(SOC_SERIES_APM32E1)
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TMR_ConfigUPdateRequest(tmr, TMR_UPDATE_SOURCE_REGULAR);
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#else
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TMR_ConfigUpdateRequest(tmr, TMR_UPDATE_SOURCE_REGULAR);
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#endif /* SOC_SERIES_APM32E1 */
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#endif /* SOC_SERIES_APM32F0 */
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return result;
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}
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static rt_uint32_t timer_clock_get(TMR_T *tmr)
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{
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#if defined(SOC_SERIES_APM32F0)
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uint32_t pclk1;
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pclk1 = RCM_ReadPCLKFreq();
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return (rt_uint32_t)(pclk1 * ((RCM->CFG1_B.APB1PSC != 0) ? 2 : 1));
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#endif /* SOC_SERIES_APM32F0 */
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#if defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1) \
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|| defined(SOC_SERIES_APM32F4)
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uint32_t pclk1, pclk2;
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RCM_ReadPCLKFreq(&pclk1, &pclk2);
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#if defined(SOC_SERIES_APM32S1)
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if (tmr == TMR1)
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#else
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if (tmr == TMR1 || tmr == TMR8 || tmr == TMR9 || tmr == TMR10 || tmr == TMR11)
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#endif /* SOC_SERIES_APM32S1 */
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{
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return (rt_uint32_t)(pclk2 * ((RCM->CFG_B.APB2PSC != 0) ? 2 : 1));
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}
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else
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{
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return (rt_uint32_t)(pclk1 * ((RCM->CFG_B.APB1PSC != 0) ? 2 : 1));
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}
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#endif
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}
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static rt_err_t drv_pwm_enable(TMR_T *tmr, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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{
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rt_uint32_t channel = (configuration->channel - 1) << 2;
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if (enable)
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{
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if (configuration->complementary)
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{
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TMR_EnableCCxNChannel(tmr, (TMR_CHANNEL_T)(0x01 << (channel & 0x1FU)));
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}
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else
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{
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TMR_EnableCCxChannel(tmr, (TMR_CHANNEL_T)(0x01 << (channel & 0x1FU)));
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}
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#if defined(SOC_SERIES_APM32F0)
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if (tmr == TMR1 || tmr == TMR15 || tmr == TMR16 || tmr == TMR17)
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#elif defined(SOC_SERIES_APM32S1)
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if (tmr == TMR1)
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#elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32F4)
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if (tmr == TMR1 || tmr == TMR8)
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#endif
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{
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TMR_EnablePWMOutputs(tmr);
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}
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TMR_Enable(tmr);
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}
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else
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{
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if (configuration->complementary)
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{
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TMR_DisableCCxNChannel(tmr, (TMR_CHANNEL_T)(0x01 << (channel & 0x1FU)));
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}
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else
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{
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TMR_DisableCCxChannel(tmr, (TMR_CHANNEL_T)(0x01 << (channel & 0x1FU)));
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}
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#if defined(SOC_SERIES_APM32F0)
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if (tmr == TMR1 || tmr == TMR15 || tmr == TMR16 || tmr == TMR17)
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#elif defined(SOC_SERIES_APM32S1)
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if (tmr == TMR1)
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#elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32F4)
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if (tmr == TMR1 || tmr == TMR8)
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#endif
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{
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TMR_DisablePWMOutputs(tmr);
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}
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TMR_Disable(tmr);
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}
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return RT_EOK;
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}
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static rt_err_t drv_pwm_get(TMR_T *tmr, struct rt_pwm_configuration *configuration)
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{
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/* Converts the channel number to the channel number of library */
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rt_uint32_t channel = (configuration->channel - 1) << 2;
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rt_uint64_t timer_clock;
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rt_uint32_t timer_reload, timer_psc;
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timer_clock = timer_clock_get(tmr);
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#if defined(SOC_SERIES_APM32F0)
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if (tmr->CTRL1_B.CLKDIV == TMR_CKD_DIV2)
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#else
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if (tmr->CTRL1_B.CLKDIV == TMR_CLOCK_DIV_2)
|
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#endif
|
|
{
|
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timer_clock = timer_clock / 2;
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}
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#if defined(SOC_SERIES_APM32F0)
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if (tmr->CTRL1_B.CLKDIV == TMR_CKD_DIV4)
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#else
|
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else if (tmr->CTRL1_B.CLKDIV == TMR_CLOCK_DIV_4)
|
|
#endif
|
|
{
|
|
timer_clock = timer_clock / 4;
|
|
}
|
|
|
|
uint32_t temp;
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temp = (uint32_t)tmr;
|
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temp += (uint32_t)(0x34 + channel);
|
|
/* Convert nanosecond to frequency and duty cycle.*/
|
|
timer_clock /= 1000000UL;
|
|
|
|
timer_reload = tmr->AUTORLD;
|
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timer_psc = tmr->PSC;
|
|
configuration->period = (timer_reload + 1) * (timer_psc + 1) * 1000UL / timer_clock;
|
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configuration->pulse = ((*(__IO uint32_t *)temp) + 1) * (timer_psc + 1) * 1000UL / timer_clock;
|
|
|
|
return RT_EOK;
|
|
}
|
|
|
|
static rt_err_t drv_pwm_set(TMR_T *tmr, struct rt_pwm_configuration *configuration)
|
|
{
|
|
rt_uint32_t period, pulse;
|
|
rt_uint64_t timer_clock, psc;
|
|
rt_uint32_t channel = 0x04 * (configuration->channel - 1);
|
|
uint32_t temp = (uint32_t)tmr;
|
|
|
|
timer_clock = timer_clock_get(tmr);
|
|
|
|
/* Convert nanosecond to frequency and duty cycle. */
|
|
timer_clock /= 1000000UL;
|
|
period = (unsigned long long)configuration->period * timer_clock / 1000ULL ;
|
|
psc = period / MAX_PERIOD + 1;
|
|
period = period / psc;
|
|
tmr->PSC = (uint16_t)(psc - 1);
|
|
|
|
if (period < MIN_PERIOD)
|
|
{
|
|
period = MIN_PERIOD;
|
|
}
|
|
tmr->AUTORLD = (uint16_t)(period - 1);
|
|
|
|
pulse = (unsigned long long)configuration->pulse * timer_clock / psc / 1000ULL;
|
|
if (pulse < MIN_PULSE)
|
|
{
|
|
pulse = MIN_PULSE;
|
|
}
|
|
else if (pulse > period)
|
|
{
|
|
pulse = period;
|
|
}
|
|
|
|
temp += (uint32_t)(0x34 + channel);
|
|
*(__IO uint32_t *)temp = pulse - 1;
|
|
|
|
tmr->CNT = 0;
|
|
|
|
/* Update frequency value */
|
|
TMR_GenerateEvent(tmr, TMR_EVENT_UPDATE);
|
|
|
|
return RT_EOK;
|
|
}
|
|
|
|
static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
|
|
{
|
|
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
|
|
TMR_T *tmr = (TMR_T *)device->parent.user_data;
|
|
|
|
switch (cmd)
|
|
{
|
|
case PWMN_CMD_ENABLE:
|
|
configuration->complementary = RT_TRUE;
|
|
case PWM_CMD_ENABLE:
|
|
return drv_pwm_enable(tmr, configuration, RT_TRUE);
|
|
case PWMN_CMD_DISABLE:
|
|
configuration->complementary = RT_FALSE;
|
|
case PWM_CMD_DISABLE:
|
|
return drv_pwm_enable(tmr, configuration, RT_FALSE);
|
|
case PWM_CMD_SET:
|
|
return drv_pwm_set(tmr, configuration);
|
|
case PWM_CMD_GET:
|
|
return drv_pwm_get(tmr, configuration);
|
|
default:
|
|
return -RT_EINVAL;
|
|
}
|
|
}
|
|
|
|
static const struct rt_pwm_ops drv_pwm_ops =
|
|
{
|
|
drv_pwm_control
|
|
};
|
|
|
|
static int rt_hw_pwm_init(void)
|
|
{
|
|
rt_uint32_t i = 0;
|
|
rt_err_t result = RT_EOK;
|
|
|
|
pwm_channel_init();
|
|
|
|
for (i = 0; i < sizeof(pwm_config) / sizeof(pwm_config[0]); i++)
|
|
{
|
|
/* pwm init */
|
|
if (apm32_pwm_hw_init(&pwm_config[i]) != RT_EOK)
|
|
{
|
|
LOG_E("%s init failed", pwm_config[i].name);
|
|
return -RT_ERROR;
|
|
}
|
|
else
|
|
{
|
|
LOG_D("%s init success", pwm_config[i].name);
|
|
|
|
/* register pwm device */
|
|
if (rt_device_pwm_register(&pwm_config[i].pwm_device, pwm_config[i].name, &drv_pwm_ops, pwm_config[i].tmr) == RT_EOK)
|
|
{
|
|
LOG_D("%s register success", pwm_config[i].name);
|
|
}
|
|
else
|
|
{
|
|
LOG_E("%s register failed", pwm_config[i].name);
|
|
result = -RT_ERROR;
|
|
}
|
|
}
|
|
}
|
|
|
|
return result;
|
|
}
|
|
INIT_DEVICE_EXPORT(rt_hw_pwm_init);
|
|
|
|
#endif /* RT_USING_PWM */
|