305 lines
19 KiB
C
305 lines
19 KiB
C
/***********************************************************************************************************************
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* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
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*
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* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
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* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
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* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
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* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
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* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
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* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
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* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
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* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
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* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
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* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
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* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
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* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
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* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
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* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
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**********************************************************************************************************************/
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#ifndef FSP_FEATURES_H
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#define FSP_FEATURES_H
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/***********************************************************************************************************************
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* Includes <System Includes> , "Project Includes"
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**********************************************************************************************************************/
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/* C99 includes. */
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#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#include <assert.h>
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/* Different compiler support. */
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#include "fsp_common_api.h"
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#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h"
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/*******************************************************************************************************************//**
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* @addtogroup BSP_MCU
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* @{
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**********************************************************************************************************************/
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/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/** Available modules. */
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typedef enum e_fsp_ip
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{
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FSP_IP_CFLASH = 0, ///< Code Flash
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FSP_IP_DFLASH = 1, ///< Data Flash
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FSP_IP_RAM = 2, ///< RAM
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FSP_IP_LVD = 3, ///< Low Voltage Detection
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FSP_IP_CGC = 3, ///< Clock Generation Circuit
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FSP_IP_LPM = 3, ///< Low Power Modes
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FSP_IP_FCU = 4, ///< Flash Control Unit
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FSP_IP_ICU = 6, ///< Interrupt Control Unit
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FSP_IP_DMAC = 7, ///< DMA Controller
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FSP_IP_DTC = 8, ///< Data Transfer Controller
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FSP_IP_IOPORT = 9, ///< I/O Ports
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FSP_IP_PFS = 10, ///< Pin Function Select
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FSP_IP_ELC = 11, ///< Event Link Controller
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FSP_IP_MPU = 13, ///< Memory Protection Unit
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FSP_IP_MSTP = 14, ///< Module Stop
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FSP_IP_MMF = 15, ///< Memory Mirror Function
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FSP_IP_KEY = 16, ///< Key Interrupt Function
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FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit
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FSP_IP_DOC = 18, ///< Data Operation Circuit
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FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator
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FSP_IP_SCI = 20, ///< Serial Communications Interface
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FSP_IP_IIC = 21, ///< I2C Bus Interface
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FSP_IP_SPI = 22, ///< Serial Peripheral Interface
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FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit
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FSP_IP_SCE = 24, ///< Secure Cryptographic Engine
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FSP_IP_SLCDC = 25, ///< Segment LCD Controller
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FSP_IP_AES = 26, ///< Advanced Encryption Standard
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FSP_IP_TRNG = 27, ///< True Random Number Generator
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FSP_IP_FCACHE = 30, ///< Flash Cache
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FSP_IP_SRAM = 31, ///< SRAM
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FSP_IP_ADC = 32, ///< A/D Converter
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FSP_IP_DAC = 33, ///< 12-Bit D/A Converter
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FSP_IP_TSN = 34, ///< Temperature Sensor
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FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit
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FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator
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FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator
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FSP_IP_OPAMP = 38, ///< Operational Amplifier
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FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter
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FSP_IP_RTC = 40, ///< Real Time Clock
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FSP_IP_WDT = 41, ///< Watch Dog Timer
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FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer
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FSP_IP_GPT = 43, ///< General PWM Timer
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FSP_IP_POEG = 44, ///< Port Output Enable for GPT
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FSP_IP_OPS = 45, ///< Output Phase Switch
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FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer
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FSP_IP_CAN = 48, ///< Controller Area Network
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FSP_IP_IRDA = 49, ///< Infrared Data Association
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FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface
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FSP_IP_USBFS = 51, ///< USB Full Speed
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FSP_IP_SDHI = 52, ///< SD/MMC Host Interface
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FSP_IP_SRC = 53, ///< Sampling Rate Converter
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FSP_IP_SSI = 54, ///< Serial Sound Interface
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FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface
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FSP_IP_ETHER = 64, ///< Ethernet MAC Controller
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FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller
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FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller
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FSP_IP_PDC = 66, ///< Parallel Data Capture Unit
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FSP_IP_GLCDC = 67, ///< Graphics LCD Controller
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FSP_IP_DRW = 68, ///< 2D Drawing Engine
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FSP_IP_JPEG = 69, ///< JPEG
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FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter
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FSP_IP_USBHS = 71, ///< USB High Speed
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FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface
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FSP_IP_CEC = 73, ///< HDMI CEC
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FSP_IP_TFU = 74, ///< Trigonometric Function Unit
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FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator
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FSP_IP_CANFD = 76, ///< CAN-FD
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FSP_IP_ULPT = 77, ///< Ultra Low Power Timer ULPT
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} fsp_ip_t;
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/** Signals that can be mapped to an interrupt. */
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typedef enum e_fsp_signal
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{
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FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH
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FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH
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FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END
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FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B
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FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A
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FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B
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FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ
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FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ
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FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A
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FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B
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FSP_SIGNAL_AGT_INT, ///< AGT INT
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FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR
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FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END
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FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW
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FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR
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FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX
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FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX
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FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX
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FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX
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FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP
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FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST
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FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1
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FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2
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FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD
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FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT
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FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT
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FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT
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FSP_SIGNAL_CTSU_END = 0, ///< CTSU END
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FSP_SIGNAL_CTSU_READ, ///< CTSU READ
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FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE
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FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI
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FSP_SIGNAL_DALI_CLI, ///< DALI CLI
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FSP_SIGNAL_DALI_SDI, ///< DALI SDI
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FSP_SIGNAL_DALI_BPI, ///< DALI BPI
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FSP_SIGNAL_DALI_FEI, ///< DALI FEI
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FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI
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FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT
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FSP_SIGNAL_DOC_INT = 0, ///< DOC INT
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FSP_SIGNAL_DRW_INT = 0, ///< DRW INT
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FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE
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FSP_SIGNAL_DTC_END, ///< DTC END
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FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT
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FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0
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FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1
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FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS
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FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT
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FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT
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FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL
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FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE
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FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL
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FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE
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FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL
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FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE
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FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL
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FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE
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FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL
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FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE
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FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL
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FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE
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FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR
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FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI
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FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT
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FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1
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FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2
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FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A
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FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B
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FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C
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FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D
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FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E
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FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F
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FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW
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FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW
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FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A
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FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B
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FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE
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FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0
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FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1
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FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2
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FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3
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FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4
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FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5
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FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6
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FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7
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FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8
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FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9
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FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10
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FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11
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FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12
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FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13
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FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14
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FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15
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FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL
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FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI
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FSP_SIGNAL_IIC_RXI, ///< IIC RXI
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FSP_SIGNAL_IIC_TEI, ///< IIC TEI
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FSP_SIGNAL_IIC_TXI, ///< IIC TXI
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FSP_SIGNAL_IIC_WUI, ///< IIC WUI
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FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1
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FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2
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FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3
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FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4
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FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B
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FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C
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FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D
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FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E
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FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW
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FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI
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FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI
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FSP_SIGNAL_KEY_INT = 0, ///< KEY INT
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FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END
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FSP_SIGNAL_PDC_INT, ///< PDC INT
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FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY
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FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT
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FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT
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FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM
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FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD
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FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY
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FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY
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FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY
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FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG
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FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY
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FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0
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FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1
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FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK
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FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY
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FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0
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FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1
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FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4
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FSP_SIGNAL_SCI_AM = 0, ///< SCI AM
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FSP_SIGNAL_SCI_ERI, ///< SCI ERI
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FSP_SIGNAL_SCI_RXI, ///< SCI RXI
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FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI
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FSP_SIGNAL_SCI_TEI, ///< SCI TEI
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FSP_SIGNAL_SCI_TXI, ///< SCI TXI
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FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI
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FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND
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FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND
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FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS
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FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD
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FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ
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FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO
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FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI
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FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE
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FSP_SIGNAL_SPI_RXI, ///< SPI RXI
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FSP_SIGNAL_SPI_TEI, ///< SPI TEI
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FSP_SIGNAL_SPI_TXI, ///< SPI TXI
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FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END
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FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY
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FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL
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FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW
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FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW
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FSP_SIGNAL_SSI_INT = 0, ///< SSI INT
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FSP_SIGNAL_SSI_RXI, ///< SSI RXI
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FSP_SIGNAL_SSI_TXI, ///< SSI TXI
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FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI
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FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ
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FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0
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FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1
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FSP_SIGNAL_USB_INT, ///< USB INT
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FSP_SIGNAL_USB_RESUME, ///< USB RESUME
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FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME
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FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW
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FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A
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FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B
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FSP_SIGNAL_ULPT_INT, ///< ULPT INT
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} fsp_signal_t;
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typedef void (* fsp_vector_t)(void);
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/** @} (end addtogroup BSP_MCU) */
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/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif
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