362 lines
17 KiB
C
362 lines
17 KiB
C
/**********************************************************************
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* $Id$ lpc177x_8x_emc.h 2011-06-02
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*//**
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* @file lpc177x_8x_emc.h
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* @brief Contains all macro definitions and function prototypes
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* support for EMC firmware library on LPC177x_8x
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* @version 1.0
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* @date 02. June. 2011
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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**********************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup EMC EMC (External Memory Controller)
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* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
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* @{
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*/
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#ifndef __LPC177X_8X_EMC_H_
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#define __LPC177X_8X_EMC_H_
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#include "lpc_types.h"
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#include "LPC177x_8x.h"
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/** @defgroup EMC_Private_Macros EMC Private Macros
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* @{
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*/
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/***********************************************************************
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* EMC Control Register (EMCControl)
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**********************************************************************/
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/* Control register mask */
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#define EMC_Control_MASK ((uint32_t )0x07)
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/* Control register EMC: Enable control. */
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#define EMC_Control_E ((uint32_t )(1<<0))
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/* Control register EMC: Address mirror control. */
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#define EMC_Control_M ((uint32_t )(1<<1))
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/* Control register EMC: Low-power mode control. */
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#define EMC_Control_L ((uint32_t )(1<<2))
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/***********************************************************************
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* EMC Status Register (EMCStatus)
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**********************************************************************/
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/* Status register mask */
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#define EMC_Status_MASK ((uint32_t )0x07)
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/* Status register EMC: Busy. */
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#define EMC_Status_B ((uint32_t )(1<<0))
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/* Status register EMC: Write buffer status. */
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#define EMC_Status_S ((uint32_t )(1<<1))
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/* Status register EMC: Self-refresh acknowledge.. */
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#define EMC_Status_SA ((uint32_t )(1<<2))
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/***********************************************************************
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* EMC Configuration register (EMCConfig)
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**********************************************************************/
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/* EMC Configuration register : Enable control. */
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#define EMC_Config_Endian_Mode ((uint32_t )(1<<0))
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/* EMC Configuration register: CCLK. */
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#define EMC_Config_CCLK ((uinr32_t)(1<<8))
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/* EMC Configuration register mask */
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#define EMC_Config_MASK ((uint32_t)(0x101))
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/***********************************************************************
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* Dynamic Memory Control register (EMCDynamicControl)
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**********************************************************************/
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/* Dynamic Memory Control register EMC: Dynamic memory clock enable. */
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#define EMC_DynamicControl_CE ((uint32_t )(1<<0))
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/* Dynamic Memory Control register EMC: Dynamic memory clock control */
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#define EMC_DynamicControl_CS ((uint32_t )(1<<1))
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/* Dynamic Memory Control register EMC: Self-refresh request, EMCSREFREQ*/
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#define EMC_DynamicControl_SR ((uint32_t )(1<<2))
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/* Dynamic Memory Control register EMC: Memory clock control (MMC)*/
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#define EMC_DynamicControl_MMC ((uint32_t )(1<<5))
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/* Dynamic Memory Control register EMC: SDRAM initialization*/
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#define EMC_DynamicControl_I(n) ((uint32_t )(n<<7))
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/* Dynamic Memory Control register EMC: Low-power SDRAM deep-sleep mode (DP)*/
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#define EMC_DynamicControl_DP ((uint32_t ) (1<<13))
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/***********************************************************************
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* Dynamic Memory Refresh Timer register (EMCDynamicRefresh)
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**********************************************************************/
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/* Dynamic Memory Refresh Timer register EMC: Refresh timer (REFRESH) */
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#define EMC_DynamicRefresh_REFRESH(n) ((uint32_t ) (n & 0x3ff))
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/***********************************************************************
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* Dynamic Memory Read Configuration register (EMCDynamicReadConfig)
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**********************************************************************/
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/* EMCDynamicReadConfig register EMC:Read data strategy (RD) */
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#define EMC_DynamicReadConfig_RD(n) ((uint32_t )(n & 0x03))
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/***********************************************************************
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* Dynamic Memory Percentage Command Period register (EMCDynamictRP)
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**********************************************************************/
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/* EMCDynamictRP register EMC: Precharge command period (tRP). */
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#define EMC_DynamictRP_tRP(n) ((uint32_t )(n & 0x0f))
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/***********************************************************************
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* Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS)
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**********************************************************************/
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/* EMCDynamictRAS register EMC: Active to precharge command period (tRAS) */
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#define EMC_DynamictRP_tRAS(n) ((uint32_t )(n & 0x0f))
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/***********************************************************************
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* Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR)
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**********************************************************************/
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/* EMCDynamictAPR register EMC: Last-data-out to active command time (tAPR) */
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#define EMC_DynamictAPR_tAPR(n) ((uint32_t )(n & 0x0f))
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/***********************************************************************
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* Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL)
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**********************************************************************/
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/* EMCDynamictDAL register EMC: Data-in to active command (tDAL)*/
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#define EMC_DynamictDAL_tDAL(n) ((uint32_t )(n & 0x0f))
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/***********************************************************************
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* Dynamic Memory Write Recovery Time register (EMCDynamictWR)
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**********************************************************************/
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/* EMCDynamictWR register EMC: Write recovery time (tWR)*/
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#define EMC_DynamictWR_tWR(n) (uint32_t )(n & 0x0f)
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/***********************************************************************
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* Dynamic Memory Active to Active Command Period register (EMCDynamictRC)
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**********************************************************************/
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/* EMCDynamictRC register EMC: Active to active command period (tRC)*/
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#define EMC_DynamictRC_tRC(n) (uint32_t )(n & 0x1f)
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/***********************************************************************
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* Dynamic Memory Auto-refresh Period register (EMCDynamictRFC)
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**********************************************************************/
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/* EMCDynamictRFC register EMC: Auto-refresh period and auto-refresh to active command period (tRFC)*/
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#define EMC_DynamictRFC_tRFC(n) ((uint32_t )(n & 0x1f))
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/***********************************************************************
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* Dynamic Memory Exit Self-refresh register (EMCDynamictXSR)
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**********************************************************************/
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/* EMCDynamictXSR register EMC: Exit self-refresh to active command time (tXSR)*/
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#define EMC_DynamictXSR_tXSR(n) ((uint32_t )(n & 0x1f))
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/***********************************************************************
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* Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD)
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**********************************************************************/
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/* EMCDynamictRRD register EMC: Active bank A to active bank B latency (tRRD )*/
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#define EMC_DynamictRRD_tRRD(n) ((uint32_t )(n & 0x0f))
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/***********************************************************************
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Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD)
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**********************************************************************/
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/* EMCDynamictMRD register EMC: Load mode register to active command time (tMRD)*/
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#define EMC_DynamictMRD_tMRD(n) ((uint32_t )(n & 0x1f))
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/***********************************************************************
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* Static Memory Extended Wait Register (EMCStaticExtendedWait)
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**********************************************************************/
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/* StaticExtendedWait register EMC: External wait time out. */
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#define EMC_StaticExtendedWait_EXTENDEDWAIT(n) ((uint32_t )(n & 0x3ff))
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/***********************************************************************
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* Dynamic Memory Configuration registers (EMCDynamicConfig0-3)
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**********************************************************************/
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/* DynamicConfig register EMC: Memory device (MD). */
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#define EMC_DynamicConfig_MD(n) ((uint32_t )(n << 3))
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/* DynamicConfig register EMC: Address mapping (AM) */
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#define EMC_DynamicConfig_AM1(n) ((uint32_t )(n << 7))
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/* DynamicConfig register EMC: Address mapping (AM) */
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#define EMC_DynamicConfig_AM2(n) ((uint32_t )(1 << 14))
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/* DynamicConfig register EMC: Buffer enable */
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#define EMC_DynamicConfig_B ((uint32_t )(1 << 19))
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/* DynamicConfig register EMC: Write protect (P) */
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#define EMC_DynamicConfig_P ((uint32_t )(1 << 20))
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/***********************************************************************
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* Dynamic Memory RAS & CAS Delay registers (EMCDynamicRASCAS0-3)
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**********************************************************************/
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/* DynamicRASCAS register EMC: RAS latency (active to read/write delay) (RAS). */
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#define EMC_DynamicConfig_RAS(n) ((uint32_t )(n & 0x03))
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/* DynamicRASCAS register EMC: CAS latency (CAS)*/
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#define EMC_DynamicConfig_CAS(n) ((uint32_t )(n << 8))
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/***********************************************************************
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* Static Memory Configuration registers (EMCStaticConfig0-3)
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**********************************************************************/
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/* StaticConfig register EMC: Memory width (MW). */
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#define EMC_StaticConfig_MW(n) ((uint32_t )(n & 0x03))
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/* StaticConfig register EMC: Memory width 8bit . */
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#define EMC_StaticConfig_MW_8BITS (EMC_StaticConfig_MW(0))
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/* StaticConfig register EMC: Memory width 16bit . */
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#define EMC_StaticConfig_MW_16BITS (EMC_StaticConfig_MW(1))
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/* StaticConfig register EMC: Memory width 32bit . */
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#define EMC_StaticConfig_MW_32BITS (EMC_StaticConfig_MW(2))
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/* StaticConfig register EMC: Page mode (PM) */
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#define EMC_StaticConfig_PM ((uint32_t )(1 << 3))
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/* StaticConfig register EMC: Chip select polarity (PC) */
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#define EMC_StaticConfig_PC ((uint32_t )(1 << 6))
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/* StaticConfig register EMC: Byte lane state (PB) */
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#define EMC_StaticConfig_PB ((uint32_t )(1 << 7))
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/* StaticConfig register EMC: Extended wait (EW) */
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#define EMC_StaticConfig_EW ((uint32_t )(1 << 8))
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/* StaticConfig register EMC: Buffer enable (B) */
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#define EMC_StaticConfig_B ((uint32_t )(1 << 19))
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/* StaticConfig register EMC: Write protect (P) */
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#define EMC_StaticConfig_P ((uint32_t )(1 << 20))
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/***********************************************************************
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* Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3)
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**********************************************************************/
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/* StaticWaitWen register EMC: Wait write enable (WAITWEN). */
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#define EMC_StaticWaitWen_WAITWEN(n) ((uint32_t )(n & 0x0f))
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/***********************************************************************
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* Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3)
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**********************************************************************/
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/* StaticWaitOen register EMC: Wait output enable (WAITOEN). */
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#define EMC_StaticWaitOen_WAITOEN(n) ((uint32_t )(n & 0x0f))
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/***********************************************************************
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* Static Memory Read Delay registers (EMCStaticWaitRd0-3)
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**********************************************************************/
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/* StaticWaitRd register EMC: Non-page mode read wait states or asynchronous page mode
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read first access wait state (WAITRD) */
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#define EMC_StaticWaitRd_WAITRD(n) ((uint32_t )(n & 0x1f))
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/***********************************************************************
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* Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3)
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**********************************************************************/
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/* StaticwaitPage register EMC: Asynchronous page mode read after the first
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read wait states (WAITPAGE). */
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#define EMC_StaticwaitPage_WAITPAGE(n) ((uint32_t )(n & 0x1f))
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/***********************************************************************
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* Static Memory Write Delay registers (EMCStaticWaitwr0-3)
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**********************************************************************/
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/* StaticWaitwr register EMC: Write wait states (WAITWR). */
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#define EMC_StaticWaitwr_WAITWR(n) ((uint32_t )(n & 0x1f))
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/***********************************************************************
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* Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3)
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**********************************************************************/
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/* StaticWaitTurn register EMC: Bus turnaround cycles (WAITTURN). */
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#define EMC_StaticWaitTurn_WAITTURN(n) ((uint32_t )(n & 0x0f))
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/***********************************************************************
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* Delay Control register (EMCDLYCTL)
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**********************************************************************/
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#define EMC_DLYCTL_CMDDLY(n) ((uint32_t)(n&0x1F))
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#define EMC_DLYCTL_FBCLKDLY(n) ((uint32_t)((n&0x1F)<<8))
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#define EMC_DLYCTL_CLKOUT0DLY(n) ((uint32_t)((n&0x1F)<<16))
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#define EMC_DLYCTL_CLKOUT1DLY(n) ((uint32_t)((n&0x1F)<<24))
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/***********************************************************************
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* EMC Calibration register (EMCCAL)
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**********************************************************************/
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#define EMC_CAL_CALVALUE(n) ((uint32_t)(n&0xFF))
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#define EMC_CAL_START ((uint32_t)(1<<14))
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#define EMC_CAL_DONE ((uint32_t)(1<<15))
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#define EMC_LITTLE_ENDIAN_MODE ((uint32_t)(0))
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#define EMC_BIG_ENDIAN_MODE ((uint32_t)(1))
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/**
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* @}
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*/
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/* Public Types --------------------------------------------------------------- */
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/** @defgroup EMC_Public_Types EMC Public Types
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* @{
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*/
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/*EMC dynamic memory registers enum*/
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typedef enum
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{
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EMC_DYN_MEM_REFRESH_TIMER,
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EMC_DYN_MEM_READ_CONFIG,
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EMC_DYN_MEM_TRP,
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EMC_DYN_MEM_TRAS,
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EMC_DYN_MEM_TSREX,
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EMC_DYN_MEM_TAPR,
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EMC_DYN_MEM_TDAL,
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EMC_DYN_MEM_TWR,
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EMC_DYN_MEM_TRC,
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EMC_DYN_MEM_TRFC,
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EMC_DYN_MEM_TXSR,
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EMC_DYN_MEM_TRRD,
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EMC_DYN_MEM_TMRD
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} EMC_DYN_MEM_PAR;
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/*EMC static memory registers enum*/
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typedef enum
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{
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EMC_STA_MEM_WAITWEN,
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EMC_STA_MEM_WAITOEN,
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EMC_STA_MEM_WAITRD,
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EMC_STA_MEM_WAITPAGE,
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EMC_STA_MEM_WAITWR,
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EMC_STA_MEM_WAITTURN,
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} EMC_STA_MEM_PAR;
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/**
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* @}
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*/
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/* Public Functions ----------------------------------------------------------- */
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/** @defgroup EMC_Public_Functions EMC Public Functions
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* @{
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*/
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extern void EMC_Init(void);
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extern void EMC_ConfigEndianMode(uint32_t endian_mode);
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extern void EMC_DynCtrlClockEnable(uint32_t clock_enable);
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extern void EMC_DynCtrlClockControl(int32_t clock_control);
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extern void EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode);
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extern void EMC_DynCtrlMMC(uint32_t MMC_val);
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extern void EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command);
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extern void EMC_DynCtrlPowerDownMode(uint32_t SDRAM_command);
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extern void EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val);
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extern void EMC_StaticExtendedWait(uint32_t Extended_wait_time_out);
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extern void EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev);
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extern void EMC_DynMemConfigAM(uint32_t index , uint32_t add_mapped);
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extern void EMC_DynMemConfigB(uint32_t index , uint32_t buff_control);
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extern void EMC_DynMemConfigP(uint32_t index , uint32_t permission);
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extern void EMC_DynMemRAS(uint32_t index , uint32_t ras_val);
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extern void EMC_DynMemCAS(uint32_t index , uint32_t cas_val);
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extern void EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width);
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extern void EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode);
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extern void EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val);
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extern void EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val);
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extern void EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait);
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extern void EMC_StaMemConfigB(uint32_t index , uint32_t buf_val);
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extern void EMC_StaMemConfigpP(uint32_t index , uint32_t per_val);
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extern void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val);
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/**
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* @}
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*/
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#endif /* __LPC177X_8X_EMC_H_ */
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/**
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* @}
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*/
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