1306 lines
38 KiB
C
1306 lines
38 KiB
C
/**
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******************************************************************************
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* @file HAL_rcc.c
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* @author IC Applications Department
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* @version V0.8
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* @date 2019_08_02
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* @brief This file provides all the RCC firmware functions.
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******************************************************************************
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* @copy
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2016 HOLOCENE</center></h2>
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "HAL_rcc.h"
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u32 TK499_SYS_CLK = 48000000;
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u32 TK499_PLL_FACTOR = 0x00004;
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/** @addtogroup StdPeriph_Driver
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* @{
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*/
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/** @defgroup RCC
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* @brief RCC driver modules
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* @{
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*/
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/** @defgroup RCC_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup RCC_Private_Defines
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* @{
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*/
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/* ------------ RCC registers bit address in the alias region ----------- */
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#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
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/* --- CR Register ---*/
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/* Alias word address of HSION bit */
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#define CR_OFFSET (RCC_OFFSET + 0x00)
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#define HSION_BitNumber 0x00
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#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
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/* Alias word address of PLLON bit */
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#define PLLON_BitNumber 0x18
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#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
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/* Alias word address of CSSON bit */
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#define CSSON_BitNumber 0x13
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#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
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/* --- CFGR Register ---*/
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/* Alias word address of USBPRE bit */
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#define CFGR_OFFSET (RCC_OFFSET + 0x04)
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#define USBPRE_BitNumber 0x16
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#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
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/* --- BDCR Register ---*/
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/* Alias word address of RTCEN bit */
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#define BDCR_OFFSET (RCC_OFFSET + 0x20)
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#define RTCEN_BitNumber 0x0F
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#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
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/* Alias word address of BDRST bit */
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#define BDRST_BitNumber 0x10
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#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
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/* --- CSR Register ---*/
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/* Alias word address of LSION bit */
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#define CSR_OFFSET (RCC_OFFSET + 0x24)
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#define LSION_BitNumber 0x00
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#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
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/* ---------------------- RCC registers bit mask ------------------------ */
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/* CR register bit mask */
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#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
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#define CR_HSEBYP_Set ((uint32_t)0x00040000)
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#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
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#define CR_HSEON_Set ((uint32_t)0x00010000)
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#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
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/* CFGR register bit mask */
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#define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
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#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
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#define CFGR_PLLSRC_Mask ((uint32_t)0x00400000)
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#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
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#define CFGR_SWS_Mask ((uint32_t)0x0000000C)
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#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
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#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
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#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
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#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
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#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
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#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
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#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
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#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
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#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
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/* CSR register bit mask */
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#define CSR_RMVF_Set ((uint32_t)0x01000000)
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/* RCC Flag Mask */
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#define FLAG_Mask ((uint8_t)0x1F)
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/* Typical Value of the HSI in Hz */
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#define HSI_Value ((uint32_t)8000000)
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/* CIR register byte 2 (Bits[15:8]) base address */
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#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
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/* CIR register byte 3 (Bits[23:16]) base address */
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#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
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/* CFGR register byte 4 (Bits[31:24]) base address */
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#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)
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/* BDCR register base address */
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#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
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#ifndef HSEStartUp_TimeOut
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/* Time out for HSE start up */
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#define HSEStartUp_TimeOut ((uint16_t)0x0500)
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#endif
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/**
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* @}
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*/
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/** @defgroup RCC_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup RCC_Private_Variables
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* @{
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*/
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static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
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/**
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* @}
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*/
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/** @defgroup RCC_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup RCC_Private_Functions
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* @{
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*/
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void SystemClk_HSEInit(uint32_t PLL_DN)
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{
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RCC_DeInit();
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//HSE on
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//CR寄存器BIT16位（HSEON位）置1，作用是连接外部时钟HSE作为系统时钟
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RCC_HSEConfig(RCC_HSE_ON);
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while(1)
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{
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if(RCC_WaitForHSEStartUp()!=0)
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{
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break;
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}
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}
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RCC_PLLCmd(DISABLE);
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RCC_PLLConfig(RCC_PLLSource_HSE_Div1,PLL_DN);
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RCC_PLLCmd(ENABLE);
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RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);//选择外部时钟作为系统时钟
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}
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/**
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* @brief Resets the RCC clock configuration to the default reset state.
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* @param None
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* @retval : None
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*/
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void RCC_DeInit(void)
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{
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
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RCC->CFGR &= (uint32_t)0xF8FF0000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
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RCC->CFGR &= (uint32_t)0xFF80FFFF;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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}
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/**
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* @brief Configures the External High Speed oscillator (HSE).
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* HSE can not be stopped if it is used directly or through the
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* PLL as system clock.
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* @param RCC_HSE: specifies the new state of the HSE.
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* This parameter can be one of the following values:
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* @arg RCC_HSE_OFF: HSE oscillator OFF
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* @arg RCC_HSE_ON: HSE oscillator ON
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* @arg RCC_HSE_Bypass: HSE oscillator bypassed with external
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* clock
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* @retval : None
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*/
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void RCC_HSEConfig(uint32_t RCC_HSE)
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{
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/* Check the parameters */
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assert_param(IS_RCC_HSE(RCC_HSE));
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/* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
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/* Reset HSEON bit */
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RCC->CR &= CR_HSEON_Reset;
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/* Reset HSEBYP bit */
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RCC->CR &= CR_HSEBYP_Reset;
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/* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
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switch(RCC_HSE)
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{
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case RCC_HSE_ON:
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/* Set HSEON bit */
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RCC->CR |= CR_HSEON_Set;
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break;
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case RCC_HSE_Bypass:
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/* Set HSEBYP and HSEON bits */
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RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
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break;
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default:
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break;
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}
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}
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/**
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* @brief Waits for HSE start-up.
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* @param None
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* @retval : An ErrorStatus enumuration value:
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* - SUCCESS: HSE oscillator is stable and ready to use
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* - ERROR: HSE oscillator not yet ready
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*/
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ErrorStatus RCC_WaitForHSEStartUp(void)
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{
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__IO uint32_t StartUpCounter = 0;
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ErrorStatus status = ERROR;
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FlagStatus HSEStatus = RESET;
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
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StartUpCounter++;
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} while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut));
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if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
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{
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status = SUCCESS;
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}
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else
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{
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status = ERROR;
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}
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return (status);
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}
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/**
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* @brief Adjusts the Internal High Speed oscillator (HSI) calibration
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* value.
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* @param HSICalibrationValue: specifies the calibration trimming value.
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* This parameter must be a number between 0 and 0x1F.
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* @retval : None
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*/
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void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
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tmpreg = RCC->CR;
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/* Clear HSITRIM[4:0] bits */
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tmpreg &= CR_HSITRIM_Mask;
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/* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
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tmpreg |= (uint32_t)HSICalibrationValue << 3;
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/* Store the new value */
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RCC->CR = tmpreg;
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}
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/**
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* @brief Enables or disables the Internal High Speed oscillator (HSI).
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* HSI can not be stopped if it is used directly or through the
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* PLL as system clock.
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* @param NewState: new state of the HSI.
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* This parameter can be: ENABLE or DISABLE.
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* @retval : None
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*/
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void RCC_HSICmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if(NewState==ENABLE)
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{
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RCC->CR |= 0x01;
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}
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else
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{
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RCC->CR &= 0xfffffffe;
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}
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}
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/**
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* @brief Configures the PLL clock source and DM DN factor.
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* This function must be used only when the PLL is disabled.
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* @param RCC_PLLSource: specifies the PLL entry clock source.
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* This parameter can be one of the following values:
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* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
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* by 2 selected as PLL clock entry
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* @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
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* as PLL clock entry
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* @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
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* by 2 selected as PLL clock entry
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* @param RCC_PLLDN: specifies the PLL multiplication factor.
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* This parameter can be RCC_PLLMul_x where x:[31:26]
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* @param RCC_PLLDM: specifies the PLL Divsior factor.
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* This parameter can be RCC_Divsior_x where x:[22:20]
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* @retval : None
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*/
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void RCC_PLLDMDNConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLDN,uint32_t RCC_PLLDP, uint32_t RCC_PLLDM)
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{
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uint32_t tmpreg0 = 0;
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/* Check the parameters */
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assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
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assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
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if(RCC_PLLSource == 0)
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{
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tmpreg0 &= ~(1<<22);
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}
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else
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{
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TK499_PLL_FACTOR |= 0x10000;
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tmpreg0 |= (1<<22);
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}
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RCC_PLLDN &= 0x7f;
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RCC_PLLDP &= 0x3;
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RCC_PLLDM &= 0xf;
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/* Set the PLL configuration bits */
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tmpreg0 |= (u32)((u32)(RCC_PLLDN<<6))|((u32)(RCC_PLLDP<<4))|((u32)RCC_PLLDM);
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RCC->PLLCFGR = tmpreg0;
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// RCC->PLLCFGR = 0x4004d1;
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}
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/**
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* @brief Configures the PLL clock source and multiplication factor.
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* This function must be used only when the PLL is disabled.
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* @param RCC_PLLSource: specifies the PLL entry clock source.
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* This parameter can be one of the following values:
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* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
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* by 2 selected as PLL clock entry
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* @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
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* as PLL clock entry
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* @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
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* by 2 selected as PLL clock entry
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* @param RCC_PLLMul: specifies the PLL multiplication factor.
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* This parameter can be RCC_PLLMul_x where x:[31:26][22:20]
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* @retval : None
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*/
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void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
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assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
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tmpreg = RCC->CFGR;
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/* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
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tmpreg &= CFGR_PLL_Mask;
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/* Set the PLL configuration bits */
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tmpreg |= RCC_PLLSource;
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/* Store the new value */
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RCC->CFGR = tmpreg;
|
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if(RCC_PLLMul==RCC_PLLMul_2)
|
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{
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TK499_PLL_FACTOR = 2;
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RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000001, 0x00000000,0x00000000); //Frclk*8/4
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}
|
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if(RCC_PLLMul==RCC_PLLMul_3)
|
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{
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TK499_PLL_FACTOR = 3;
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RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000002, 0x00000000,0x00000000);//Frclk*6/2
|
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}
|
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if(RCC_PLLMul==RCC_PLLMul_4)
|
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{
|
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TK499_PLL_FACTOR = 4;
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RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000003, 0x00000000,0x00000000);//Frclk*8/2
|
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}
|
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if(RCC_PLLMul==RCC_PLLMul_5)
|
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{
|
||
TK499_PLL_FACTOR = 5;
|
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RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000013, 0x00000001,0x00000001);//Frclk*10/2
|
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}
|
||
if(RCC_PLLMul==RCC_PLLMul_6)
|
||
{
|
||
TK499_PLL_FACTOR = 6;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000005, 0x00000000,0x00000000);//Frclk*12/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_7)
|
||
{
|
||
TK499_PLL_FACTOR = 7;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000006, 0x00000000,0x00000000);//Frclk*14/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_8)
|
||
{
|
||
TK499_PLL_FACTOR = 8;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000007, 0x00000000,0x00000000);//Frclk*16/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_9)
|
||
{
|
||
TK499_PLL_FACTOR = 9;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000008, 0x00000000,0x00000000);//Frclk*18/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_10)
|
||
{
|
||
TK499_PLL_FACTOR = 10;
|
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RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000009, 0x00000000,0x00000000);//Frclk*20/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_11)
|
||
{
|
||
TK499_PLL_FACTOR = 11;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000a, 0x00000000,0x00000000);//Frclk*22/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_12)
|
||
{
|
||
TK499_PLL_FACTOR = 12;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000b, 0x00000000,0x00000000);//Frclk*24/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_13)
|
||
{
|
||
TK499_PLL_FACTOR = 13;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000c, 0x00000000,0x00000000);//Frclk*26/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_14)
|
||
{
|
||
TK499_PLL_FACTOR = 14;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000d, 0x00000000,0x00000000);//Frclk*28/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_15)
|
||
{
|
||
TK499_PLL_FACTOR = 15;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000e, 0x00000000,0x00000000);//Frclk*30/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_16)
|
||
{
|
||
TK499_PLL_FACTOR = 16;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000f, 0x00000000,0x00000000);//Frclk*32/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_17)
|
||
{
|
||
TK499_PLL_FACTOR = 17;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000010, 0x00000000,0x00000000);//Frclk*32/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_18)
|
||
{
|
||
TK499_PLL_FACTOR = 18;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000011, 0x00000000,0x00000000);//Frclk*32/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_19)
|
||
{
|
||
TK499_PLL_FACTOR = 19;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000012, 0x00000000,0x00000000);//Frclk*32/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_20)
|
||
{
|
||
TK499_PLL_FACTOR = 20;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000013, 0x00000000,0x00000000);//Frclk*32/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_21)
|
||
{
|
||
TK499_PLL_FACTOR = 21;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000014, 0x00000000,0x00000000);//Frclk*32/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_22)
|
||
{
|
||
TK499_PLL_FACTOR = 22;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000015, 0x00000000,0x00000000);//Frclk*32/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_23)
|
||
{
|
||
TK499_PLL_FACTOR = 23;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000016, 0x00000000,0x00000000);//Frclk*32/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_24)
|
||
{
|
||
TK499_PLL_FACTOR = 24;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000017, 0x00000000,0x00000000);//Frclk*32/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_25)
|
||
{
|
||
TK499_PLL_FACTOR = 25;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000018, 0x00000000,0x00000000);//Frclk*32/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_26)
|
||
{
|
||
TK499_PLL_FACTOR = 26;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000019, 0x00000000,0x00000000);//Frclk*32/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_27)
|
||
{
|
||
TK499_PLL_FACTOR = 27;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000020, 0x00000000,0x00000000);//Frclk*32/2
|
||
}
|
||
if(RCC_PLLMul==RCC_PLLMul_28)
|
||
{
|
||
TK499_PLL_FACTOR = 28;
|
||
RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000021, 0x00000000,0x00000000);//Frclk*32/2
|
||
}
|
||
}
|
||
|
||
|
||
/**
|
||
* @brief Enables or disables the PLL.
|
||
* The PLL can not be disabled if it is used as system clock.
|
||
* @param NewState: new state of the PLL.
|
||
* This parameter can be: ENABLE or DISABLE.
|
||
* @retval : None
|
||
*/
|
||
void RCC_PLLCmd(FunctionalState NewState)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||
|
||
if (NewState != DISABLE)
|
||
{
|
||
RCC->CR |= 0x01000000;
|
||
}
|
||
else
|
||
{
|
||
RCC->CR &= 0xfeffffff;
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @brief Configures the system clock (SYSCLK).
|
||
* @param RCC_SYSCLKSource: specifies the clock source used as system
|
||
* clock. This parameter can be one of the following values:
|
||
* @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
|
||
* @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
|
||
* @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
|
||
* @retval : None
|
||
*/
|
||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
|
||
{
|
||
uint32_t tmpreg = 0;
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
|
||
tmpreg = RCC->CFGR;
|
||
/* Clear SW[1:0] bits */
|
||
tmpreg &= CFGR_SW_Mask;
|
||
/* Set SW[1:0] bits according to RCC_SYSCLKSource value */
|
||
tmpreg |= RCC_SYSCLKSource;
|
||
/* Store the new value */
|
||
RCC->CFGR = tmpreg;
|
||
if(RCC_SYSCLKSource == RCC_SYSCLKSource_PLLCLK)
|
||
{
|
||
if(TK499_PLL_FACTOR&0x10000)//hse as pll src
|
||
{
|
||
TK499_SYS_CLK = (TK499_PLL_FACTOR&0xff)*HSE_VALUE;
|
||
}
|
||
else
|
||
{
|
||
TK499_SYS_CLK = (TK499_PLL_FACTOR&0xff)*HSI_Value_Pll_ON;
|
||
}
|
||
}
|
||
else if(RCC_SYSCLKSource == RCC_SYSCLKSource_HSE)
|
||
{
|
||
TK499_SYS_CLK = HSE_VALUE;
|
||
}
|
||
else
|
||
{
|
||
TK499_SYS_CLK = HSI_Value_Pll_OFF;
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @brief Returns the clock source used as system clock.
|
||
* @param None
|
||
* @retval : The clock source used as system clock. The returned value can
|
||
* be one of the following:
|
||
* - 0x00: HSI/6 used as system clock
|
||
* - 0x04: HSE used as system clock
|
||
* - 0x08: PLL used as system clock
|
||
*/
|
||
uint8_t RCC_GetSYSCLKSource(void)
|
||
{
|
||
return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
|
||
}
|
||
|
||
/**
|
||
* @brief Configures the AHB clock (HCLK).
|
||
* @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
|
||
* the system clock (SYSCLK).
|
||
* This parameter can be one of the following values:
|
||
* @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
|
||
* @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
|
||
* @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
|
||
* @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
|
||
* @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
|
||
* @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
|
||
* @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
|
||
* @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
|
||
* @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
|
||
* @retval : None
|
||
*/
|
||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
|
||
{
|
||
uint32_t tmpreg = 0;
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_HCLK(RCC_SYSCLK));
|
||
tmpreg = RCC->CFGR;
|
||
/* Clear HPRE[3:0] bits */
|
||
tmpreg &= CFGR_HPRE_Reset_Mask;
|
||
/* Set HPRE[3:0] bits according to RCC_SYSCLK value */
|
||
tmpreg |= RCC_SYSCLK;
|
||
/* Store the new value */
|
||
RCC->CFGR = tmpreg;
|
||
}
|
||
|
||
/**
|
||
* @brief Configures the Low Speed APB clock (PCLK1).
|
||
* @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
|
||
* the AHB clock (HCLK).
|
||
* This parameter can be one of the following values:
|
||
* @arg RCC_HCLK_Div1: APB1 clock = HCLK
|
||
* @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
|
||
* @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
|
||
* @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
|
||
* @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
|
||
* @retval : None
|
||
*/
|
||
void RCC_PCLK1Config(uint32_t RCC_HCLK)
|
||
{
|
||
uint32_t tmpreg = 0;
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_PCLK(RCC_HCLK));
|
||
tmpreg = RCC->CFGR;
|
||
/* Clear PPRE1[2:0] bits */
|
||
tmpreg &= CFGR_PPRE1_Reset_Mask;
|
||
/* Set PPRE1[2:0] bits according to RCC_HCLK value */
|
||
tmpreg |= RCC_HCLK;
|
||
/* Store the new value */
|
||
RCC->CFGR = tmpreg;
|
||
}
|
||
|
||
/**
|
||
* @brief Configures the High Speed APB clock (PCLK2).
|
||
* @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
|
||
* the AHB clock (HCLK).
|
||
* This parameter can be one of the following values:
|
||
* @arg RCC_HCLK_Div1: APB2 clock = HCLK
|
||
* @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
|
||
* @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
|
||
* @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
|
||
* @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
|
||
* @retval : None
|
||
*/
|
||
void RCC_PCLK2Config(uint32_t RCC_HCLK)
|
||
{
|
||
uint32_t tmpreg = 0;
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_PCLK(RCC_HCLK));
|
||
tmpreg = RCC->CFGR;
|
||
/* Clear PPRE2[2:0] bits */
|
||
tmpreg &= CFGR_PPRE2_Reset_Mask;
|
||
/* Set PPRE2[2:0] bits according to RCC_HCLK value */
|
||
tmpreg |= RCC_HCLK << 3;
|
||
/* Store the new value */
|
||
RCC->CFGR = tmpreg;
|
||
}
|
||
|
||
/**
|
||
* @brief Enables or disables the specified RCC interrupts.
|
||
* @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
|
||
* This parameter can be any combination of the following values:
|
||
* @arg RCC_IT_LSIRDY: LSI ready interrupt
|
||
* @arg RCC_IT_LSERDY: LSE ready interrupt
|
||
* @arg RCC_IT_HSIRDY: HSI ready interrupt
|
||
* @arg RCC_IT_HSERDY: HSE ready interrupt
|
||
* @arg RCC_IT_PLLRDY: PLL ready interrupt
|
||
* @param NewState: new state of the specified RCC interrupts.
|
||
* This parameter can be: ENABLE or DISABLE.
|
||
* @retval : None
|
||
*/
|
||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_IT(RCC_IT));
|
||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||
if (NewState != DISABLE)
|
||
{
|
||
/* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
|
||
|
||
RCC->CIR |= ((uint32_t)RCC_IT)<<8;
|
||
}
|
||
else
|
||
{
|
||
/* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
|
||
|
||
RCC->CIR &= ~((uint32_t)RCC_IT<<8);
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @brief Configures the USB clock (USBCLK).
|
||
* @param RCC_USBCLKSource: specifies the USB clock source. This clock is
|
||
* derived from the PLL output.
|
||
* This parameter can be one of the following values:
|
||
* @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
|
||
* clock source
|
||
* @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
|
||
* @retval : None
|
||
*/
|
||
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
|
||
RCC->CFGR |= RCC_USBCLKSource;
|
||
}
|
||
|
||
/**
|
||
* @brief Configures the ADC clock (ADCCLK).
|
||
* @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from
|
||
* the APB2 clock (PCLK2).
|
||
* This parameter can be one of the following values:
|
||
* @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
|
||
* @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
|
||
* @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
|
||
* @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
|
||
* @retval : None
|
||
*/
|
||
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
|
||
{
|
||
uint32_t tmpreg = 0;
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
|
||
tmpreg = RCC->CFGR;
|
||
/* Clear ADCPRE[1:0] bits */
|
||
tmpreg &= CFGR_ADCPRE_Reset_Mask;
|
||
/* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
|
||
tmpreg |= RCC_PCLK2;
|
||
/* Store the new value */
|
||
RCC->CFGR = tmpreg;
|
||
}
|
||
|
||
/**
|
||
* @brief Configures the External Low Speed oscillator (LSE).
|
||
* @param RCC_LSE: specifies the new state of the LSE.
|
||
* This parameter can be one of the following values:
|
||
* @arg RCC_LSE_OFF: LSE oscillator OFF
|
||
* @arg RCC_LSE_ON: LSE oscillator ON
|
||
* @arg RCC_LSE_Bypass: LSE oscillator bypassed with external
|
||
* clock
|
||
* @retval : None
|
||
*/
|
||
void RCC_LSEConfig(uint8_t RCC_LSE)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_LSE(RCC_LSE));
|
||
/* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
|
||
/* Reset LSEON bit */
|
||
RCC->BDCR &= ~((uint32_t)RCC_LSE_ON);
|
||
/* Reset LSEBYP bit */
|
||
RCC->BDCR &= ~((uint32_t)RCC_LSE_ON);
|
||
/* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
|
||
switch(RCC_LSE)
|
||
{
|
||
case RCC_LSE_ON:
|
||
/* Set LSEON bit */
|
||
RCC->BDCR |= RCC_LSE_ON;
|
||
break;
|
||
|
||
case RCC_LSE_Bypass:
|
||
/* Set LSEBYP and LSEON bits */
|
||
RCC->BDCR |= RCC_LSE_Bypass | RCC_LSE_ON;
|
||
break;
|
||
|
||
default:
|
||
break;
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @brief Enables or disables the Internal Low Speed oscillator (LSI).
|
||
* LSI can not be disabled if the IWDG is running.
|
||
* @param NewState: new state of the LSI.
|
||
* This parameter can be: ENABLE or DISABLE.
|
||
* @retval : None
|
||
*/
|
||
void RCC_LSICmd(FunctionalState NewState)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||
|
||
if (NewState != DISABLE)
|
||
{
|
||
RCC->CSR |= 0x00000001;
|
||
}
|
||
else
|
||
{
|
||
RCC->CSR &= 0xfffffffe;
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @brief Configures the RTC clock (RTCCLK).
|
||
* Once the RTC clock is selected it can't be changed unless the
|
||
* Backup domain is reset.
|
||
* @param RCC_RTCCLKSource: specifies the RTC clock source.
|
||
* This parameter can be one of the following values:
|
||
* @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
|
||
* @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
|
||
* @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
|
||
* selected as RTC clock
|
||
* @retval : None
|
||
*/
|
||
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
|
||
/* Select the RTC clock source */
|
||
RCC->BDCR |= RCC_RTCCLKSource;
|
||
}
|
||
|
||
/**
|
||
* @brief Enables or disables the RTC clock.
|
||
* This function must be used only after the RTC clock was
|
||
* selected using the RCC_RTCCLKConfig function.
|
||
* @param NewState: new state of the RTC clock.
|
||
* This parameter can be: ENABLE or DISABLE.
|
||
* @retval : None
|
||
*/
|
||
void RCC_RTCCLKCmd(FunctionalState NewState)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||
|
||
if (NewState != DISABLE)
|
||
{
|
||
RCC->BDCR |= 0x00008000;
|
||
}
|
||
else
|
||
{
|
||
RCC->BDCR &= 0xffff7fff;
|
||
}
|
||
}
|
||
void getSystemClock(u32 *sysclk)
|
||
{
|
||
u32 tempreg0 = RCC->CFGR;
|
||
u32 tempreg1;
|
||
u8 dn,dp,dm;
|
||
if((tempreg0 & 0xC) == 0x00)
|
||
{
|
||
*sysclk = 8000000;
|
||
}
|
||
else if((tempreg0 & 0xC) ==0x04)
|
||
{
|
||
*sysclk = 12000000;
|
||
}
|
||
else
|
||
{
|
||
tempreg1 = RCC->PLLCFGR;
|
||
dn = (tempreg1 >> 6) & 0x7F;
|
||
dn ++;
|
||
dp = (tempreg1 >> 4) & 0x3;
|
||
if(dp == 0)
|
||
dp = 1;
|
||
else if(dp == 1)
|
||
dp = 2;
|
||
else if(dp == 2)
|
||
dp = 4;
|
||
else if(dp == 3)
|
||
dp = 8;
|
||
dm = (tempreg1 >> 0) & 0xF;
|
||
dm++;
|
||
if(tempreg1 & (1 << 22))
|
||
{
|
||
if(tempreg0 & (1 << 16))
|
||
*sysclk = 6000000* dn/( dm * dp);
|
||
else
|
||
*sysclk = 12000000* dn/( dm * dp);
|
||
}
|
||
else
|
||
{
|
||
*sysclk = 12000000* dn/( dm * dp);
|
||
}
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @brief Returns the frequencies of different on chip clocks.
|
||
* @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which
|
||
* will hold the clocks frequencies.
|
||
* @retval : None
|
||
*/
|
||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
|
||
{
|
||
uint32_t tmp = 0, presc = 0;
|
||
/* Get SYSCLK source -------------------------------------------------------*/
|
||
tmp = RCC->CFGR & CFGR_SWS_Mask;
|
||
switch (tmp)
|
||
{
|
||
case 0x00: /* HSI used as system clock */
|
||
RCC_Clocks->SYSCLK_Frequency = HSI_Value_Pll_OFF;
|
||
break;
|
||
case 0x04: /* HSE used as system clock */
|
||
RCC_Clocks->SYSCLK_Frequency = HSE_Value;
|
||
break;
|
||
case 0x08: /* PLL used as system clock */
|
||
/* Get PLL clock source and multiplication factor ----------------------*/
|
||
|
||
RCC_Clocks->SYSCLK_Frequency = TK499_SYS_CLK;
|
||
getSystemClock( & (RCC_Clocks->SYSCLK_Frequency ));
|
||
break;
|
||
default:
|
||
RCC_Clocks->SYSCLK_Frequency = HSI_Value_Pll_OFF;
|
||
break;
|
||
}
|
||
/* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
|
||
/* Get HCLK prescaler */
|
||
tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
|
||
tmp = tmp >> 4;
|
||
presc = APBAHBPrescTable[tmp];
|
||
/* HCLK clock frequency */
|
||
RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
|
||
/* Get PCLK1 prescaler */
|
||
tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
|
||
tmp = tmp >> 8;
|
||
presc = APBAHBPrescTable[tmp];
|
||
/* PCLK1 clock frequency */
|
||
RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
|
||
/* Get PCLK2 prescaler */
|
||
tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
|
||
tmp = tmp >> 11;
|
||
presc = APBAHBPrescTable[tmp];
|
||
/* PCLK2 clock frequency */
|
||
RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
|
||
/* Get ADCCLK prescaler */
|
||
tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
|
||
tmp = tmp >> 14;
|
||
presc = ADCPrescTable[tmp];
|
||
/* ADCCLK clock frequency */
|
||
RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
|
||
}
|
||
|
||
/**
|
||
* @brief Enables or disables the AHB peripheral clock.
|
||
* @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
|
||
* This parameter can be any combination of the following values:
|
||
* @arg RCC_AHBPeriph_DMA1
|
||
* @arg RCC_AHBPeriph_DMA2
|
||
* @arg RCC_AHBPeriph_SRAM
|
||
* @arg RCC_AHBPeriph_FLITF
|
||
* @arg RCC_AHBPeriph_CRC
|
||
* @arg RCC_AHBPeriph_FSMC
|
||
* @arg RCC_AHBPeriph_SDIO
|
||
* SRAM and FLITF clock can be disabled only during sleep mode.
|
||
* @param NewState: new state of the specified peripheral clock.
|
||
* This parameter can be: ENABLE or DISABLE.
|
||
* @retval : None
|
||
*/
|
||
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
|
||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||
if (NewState != DISABLE)
|
||
{
|
||
RCC->AHB1ENR |= RCC_AHBPeriph;
|
||
}
|
||
else
|
||
{
|
||
RCC->AHB1ENR &= ~RCC_AHBPeriph;
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @brief Enables or disables the High Speed APB (APB2) peripheral clock.
|
||
* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its
|
||
* clock.
|
||
* This parameter can be any combination of the following values:
|
||
* @arg RCC_APB2Periph_SYSCFG, RCC_AHBPeriph_GPIOA, RCC_AHBPeriph_GPIOB,
|
||
* RCC_AHBPeriph_GPIOC, RCC_AHBPeriph_GPIOD, RCC_APB2Periph_ADC1,
|
||
* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
|
||
* RCC_APB2Periph_TIM8, RCC_APB2Periph_UART1,
|
||
* RCC_APB2Periph_ALL
|
||
* @param NewState: new state of the specified peripheral clock.
|
||
* This parameter can be: ENABLE or DISABLE.
|
||
* @retval : None
|
||
*/
|
||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
|
||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||
if (NewState != DISABLE)
|
||
{
|
||
RCC->APB2ENR |= RCC_APB2Periph;
|
||
}
|
||
else
|
||
{
|
||
RCC->APB2ENR &= ~RCC_APB2Periph;
|
||
}
|
||
}
|
||
|
||
|
||
void RCC_BackupResetCmd(FunctionalState NewState)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||
*(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
|
||
}
|
||
|
||
/**
|
||
* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
|
||
* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its
|
||
* clock.
|
||
* This parameter can be any combination of the following values:
|
||
* @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
|
||
* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
|
||
* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
|
||
* RCC_APB1Periph_UART2, RCC_APB1Periph_UART3, RCC_APB1Periph_UART4,
|
||
* RCC_APB1Periph_UART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
|
||
* RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
|
||
* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL
|
||
* @param NewState: new state of the specified peripheral clock.
|
||
* This parameter can be: ENABLE or DISABLE.
|
||
* @retval : None
|
||
*/
|
||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
|
||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||
if (NewState != DISABLE)
|
||
{
|
||
RCC->APB1ENR |= RCC_APB1Periph;
|
||
}
|
||
else
|
||
{
|
||
RCC->APB1ENR &= ~RCC_APB1Periph;
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @brief Forces or releases High Speed APB (APB2) peripheral reset.
|
||
* @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
|
||
* This parameter can be any combination of the following values:
|
||
* @arg RCC_APB2Periph_AFIO, RCC_AHBPeriph_GPIOA, RCC_AHBPeriph_GPIOB,
|
||
* RCC_AHBPeriph_GPIOC, RCC_AHBPeriph_GPIOD, RCC_APB2Periph_ADC1,
|
||
* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
|
||
* RCC_APB2Periph_TIM8, RCC_APB2Periph_UART1, RCC_APB2Periph_ADC3,
|
||
* RCC_APB2Periph_ALL
|
||
* @param NewState: new state of the specified peripheral reset.
|
||
* This parameter can be: ENABLE or DISABLE.
|
||
* @retval : None
|
||
*/
|
||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
|
||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||
if (NewState != DISABLE)
|
||
{
|
||
RCC->APB2RSTR |= RCC_APB2Periph;
|
||
}
|
||
else
|
||
{
|
||
RCC->APB2RSTR &= ~RCC_APB2Periph;
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @brief Forces or releases Low Speed APB (APB1) peripheral reset.
|
||
* @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
|
||
* This parameter can be any combination of the following values:
|
||
* @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
|
||
* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
|
||
* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
|
||
* RCC_APB1Periph_UART2, RCC_APB1Periph_UART3, RCC_APB1Periph_UART4,
|
||
* RCC_APB1Periph_UART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
|
||
* RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
|
||
* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL
|
||
* @param NewState: new state of the specified peripheral clock.
|
||
* This parameter can be: ENABLE or DISABLE.
|
||
* @retval : None
|
||
*/
|
||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
|
||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||
if (NewState != DISABLE)
|
||
{
|
||
RCC->APB1RSTR |= RCC_APB1Periph;
|
||
}
|
||
else
|
||
{
|
||
RCC->APB1RSTR &= ~RCC_APB1Periph;
|
||
}
|
||
}
|
||
|
||
|
||
|
||
/**
|
||
* @brief Enables or disables the Clock Security System.
|
||
* @param NewState: new state of the Clock Security System..
|
||
* This parameter can be: ENABLE or DISABLE.
|
||
* @retval : None
|
||
*/
|
||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||
// *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
|
||
if(NewState==ENABLE)
|
||
{
|
||
RCC->CR |= (uint32_t)0x00080000;
|
||
}
|
||
else
|
||
{
|
||
RCC->CR &= (uint32_t)0xfff7ffff;
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @brief Selects the clock source to output on MCO pin.
|
||
* @param RCC_MCO: specifies the clock source to output.
|
||
* This parameter can be one of the following values:
|
||
* @arg RCC_MCO_NoClock: No clock selected
|
||
* @arg RCC_MCO_SYSCLK: System clock selected
|
||
* @arg RCC_MCO_HSI: HSI oscillator clock selected
|
||
* @arg RCC_MCO_HSE: HSE oscillator clock selected
|
||
* @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
|
||
* @retval : None
|
||
*/
|
||
void RCC_MCOConfig(uint8_t RCC_MCO)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_MCO(RCC_MCO));
|
||
/* Perform Byte access to MCO[2:0] bits to select the MCO source */
|
||
|
||
RCC->CFGR |= (RCC_MCO<<24);
|
||
}
|
||
|
||
/**
|
||
* @brief Checks whether the specified RCC flag is set or not.
|
||
* @param RCC_FLAG: specifies the flag to check.
|
||
* This parameter can be one of the following values:
|
||
* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
|
||
* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
|
||
* @arg RCC_FLAG_PLLRDY: PLL clock ready
|
||
* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
|
||
* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
|
||
* @arg RCC_FLAG_PINRST: Pin reset
|
||
* @arg RCC_FLAG_PORRST: POR/PDR reset
|
||
* @arg RCC_FLAG_SFTRST: Software reset
|
||
* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
|
||
* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
|
||
* @arg RCC_FLAG_LPWRRST: Low Power reset
|
||
* @retval : The new state of RCC_FLAG (SET or RESET).
|
||
*/
|
||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
|
||
{
|
||
uint32_t tmp = 0;
|
||
uint32_t statusreg = 0;
|
||
FlagStatus bitstatus = RESET;
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_FLAG(RCC_FLAG));
|
||
/* Get the RCC register index */
|
||
tmp = RCC_FLAG >> 5;
|
||
if (tmp == 1) /* The flag to check is in CR register */
|
||
{
|
||
statusreg = RCC->CR;
|
||
}
|
||
else if (tmp == 2) /* The flag to check is in BDCR register */
|
||
{
|
||
statusreg = RCC->BDCR;
|
||
}
|
||
else /* The flag to check is in CSR register */
|
||
{
|
||
statusreg = RCC->CSR;
|
||
}
|
||
/* Get the flag position */
|
||
tmp = RCC_FLAG & FLAG_Mask;
|
||
if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
|
||
{
|
||
bitstatus = SET;
|
||
}
|
||
else
|
||
{
|
||
bitstatus = RESET;
|
||
}
|
||
/* Return the flag status */
|
||
return bitstatus;
|
||
}
|
||
|
||
/**
|
||
* @brief Clears the RCC reset flags.
|
||
* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
|
||
* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
|
||
* RCC_FLAG_LPWRRST
|
||
* @param None
|
||
* @retval : None
|
||
*/
|
||
void RCC_ClearFlag(void)
|
||
{
|
||
/* Set RMVF bit to clear the reset flags */
|
||
RCC->CSR |= CSR_RMVF_Set;
|
||
}
|
||
|
||
/**
|
||
* @brief Checks whether the specified RCC interrupt has occurred or not.
|
||
* @param RCC_IT: specifies the RCC interrupt source to check.
|
||
* This parameter can be one of the following values:
|
||
* @arg RCC_IT_LSIRDY: LSI ready interrupt
|
||
* @arg RCC_IT_LSERDY: LSE ready interrupt
|
||
* @arg RCC_IT_HSIRDY: HSI ready interrupt
|
||
* @arg RCC_IT_HSERDY: HSE ready interrupt
|
||
* @arg RCC_IT_PLLRDY: PLL ready interrupt
|
||
* @arg RCC_IT_CSS: Clock Security System interrupt
|
||
* @retval : The new state of RCC_IT (SET or RESET).
|
||
*/
|
||
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
|
||
{
|
||
ITStatus bitstatus = RESET;
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_GET_IT(RCC_IT));
|
||
/* Check the status of the specified RCC interrupt */
|
||
if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
|
||
{
|
||
bitstatus = SET;
|
||
}
|
||
else
|
||
{
|
||
bitstatus = RESET;
|
||
}
|
||
/* Return the RCC_IT status */
|
||
return bitstatus;
|
||
}
|
||
|
||
/**
|
||
* @brief Clears the RCC's interrupt pending bits.
|
||
* @param RCC_IT: specifies the interrupt pending bit to clear.
|
||
* This parameter can be any combination of the following values:
|
||
* @arg RCC_IT_LSIRDY: LSI ready interrupt
|
||
* @arg RCC_IT_LSERDY: LSE ready interrupt
|
||
* @arg RCC_IT_HSIRDY: HSI ready interrupt
|
||
* @arg RCC_IT_HSERDY: HSE ready interrupt
|
||
* @arg RCC_IT_PLLRDY: PLL ready interrupt
|
||
* @arg RCC_IT_CSS: Clock Security System interrupt
|
||
* @retval : None
|
||
*/
|
||
void RCC_ClearITPendingBit(uint8_t RCC_IT)
|
||
{
|
||
/* Check the parameters */
|
||
assert_param(IS_RCC_CLEAR_IT(RCC_IT));
|
||
/* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
|
||
pending bits */
|
||
|
||
RCC->CIR |= (uint32_t)RCC_IT<<16;
|
||
}
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/
|