403 lines
21 KiB
C
403 lines
21 KiB
C
/*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*/
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/******************************************************************************/
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/** \file hc32f460_qspi.h
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**
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** A detailed description is available at
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** @link QspiGroup Queued SPI description @endlink
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**
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** - 2018-11-20 CDT First version for Device Driver Library of Qspi.
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**
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******************************************************************************/
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#ifndef __HC32F460_QSPI_H__
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#define __HC32F460_QSPI_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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#if (DDL_QSPI_ENABLE == DDL_ON)
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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*******************************************************************************
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** \defgroup QspiGroup Queued SPI(QSPI)
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**
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******************************************************************************/
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//@{
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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*******************************************************************************
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** \brief QSPI spi protocol enumeration
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******************************************************************************/
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typedef enum en_qspi_spi_protocol
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{
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QspiProtocolExtendSpi = 0u, ///< Extend spi protocol
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QspiProtocolTwoWiresSpi = 1u, ///< Two wires spi protocol
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QspiProtocolFourWiresSpi = 2u, ///< Four wires spi protocol
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} en_qspi_spi_protocol_t;
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/**
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*******************************************************************************
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** \brief QSPI spi Mode enumeration
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******************************************************************************/
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typedef enum en_qspi_spi_mode
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{
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QspiSpiMode0 = 0u, ///< Spi mode 0(QSCK normalcy is Low level)
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QspiSpiMode3 = 1u, ///< Spi mode 3(QSCK normalcy is High level)
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} en_qspi_spi_mode_t;
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/**
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*******************************************************************************
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** \brief QSPI bus communication mode enumeration
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******************************************************************************/
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typedef enum en_qspi_bus_mode
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{
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QspiBusModeRomAccess = 0u, ///< Rom access mode
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QspiBusModeDirectAccess = 1u, ///< Direct communication mode
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} en_qspi_bus_mode_t;
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/**
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*******************************************************************************
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** \brief QSPI prefetch data stop config enumeration
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******************************************************************************/
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typedef enum en_qspi_prefetch_config
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{
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QspiPrefetchStopComplete = 0u, ///< Stop after prefetch data complete
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QspiPrefetchStopImmediately = 1u, ///< Immediately stop prefetch
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} en_qspi_prefetch_config_t;
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/**
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*******************************************************************************
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** \brief QSPI read mode enumeration
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******************************************************************************/
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typedef enum en_qspi_read_mode
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{
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QspiReadModeStandard = 0u, ///< Standard read
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QspiReadModeFast = 1u, ///< Fast read
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QspiReadModeTwoWiresOutput = 2u, ///< Two wires output fast read
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QspiReadModeTwoWiresIO = 3u, ///< Two wires input/output fast read
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QspiReadModeFourWiresOutput = 4u, ///< Four wires output fast read
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QspiReadModeFourWiresIO = 5u, ///< Four wires input/output fast read
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QspiReadModeCustomStandard = 6u, ///< Custom standard read
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QspiReadModeCustomFast = 7u, ///< Custom fast read
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} en_qspi_read_mode_t;
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/**
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*******************************************************************************
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** \brief QSPI QSSN valid extend time enumeration
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******************************************************************************/
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typedef enum en_qspi_qssn_valid_extend_time
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{
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QspiQssnValidExtendNot = 0u, ///< Don't extend QSSN valid time
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QspiQssnValidExtendSck32 = 1u, ///< QSSN valid time extend 32 QSCK cycles
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QspiQssnValidExtendSck128 = 2u, ///< QSSN valid time extend 138 QSCK cycles
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QspiQssnValidExtendSckEver = 3u, ///< QSSN valid time extend to ever
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} en_qspi_qssn_valid_extend_time_t;
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/**
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*******************************************************************************
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** \brief QSPI QSCK duty cycle correction enumeration
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******************************************************************************/
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typedef enum en_qspi_qsck_duty_correction
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{
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QspiQsckDutyCorrNot = 0u, ///< Don't correction duty cycle
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QspiQsckDutyCorrHalfHclk = 1u, ///< QSCK's rising edge delay 0.5 HCLK cycle when Qsck select HCLK is odd
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} en_qspi_qsck_duty_correction_t;
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/**
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*******************************************************************************
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** \brief QSPI WP Pin output level enumeration
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******************************************************************************/
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typedef enum en_qspi_wp_pin_level
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{
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QspiWpPinOutputLow = 0u, ///< WP pin(QIO2) output low level
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QspiWpPinOutputHigh = 1u, ///< WP pin(QIO2) output high level
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} en_qspi_wp_pin_level_t;
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/**
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*******************************************************************************
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** \brief QSPI QSSN setup delay time enumeration
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******************************************************************************/
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typedef enum en_qspi_qssn_setup_delay
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{
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QspiQssnSetupDelayHalfQsck = 0u, ///< QSSN setup delay 0.5 QSCK output than QSCK first rising edge
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QspiQssnSetupDelay1Dot5Qsck = 1u, ///< QSSN setup delay 1.5 QSCK output than QSCK first rising edge
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} en_qspi_qssn_setup_delay_t;
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/**
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*******************************************************************************
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** \brief QSPI QSSN hold delay time enumeration
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******************************************************************************/
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typedef enum en_qspi_qssn_hold_delay
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{
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QspiQssnHoldDelayHalfQsck = 0u, ///< QSSN hold delay 0.5 QSCK release than QSCK last rising edge
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QspiQssnHoldDelay1Dot5Qsck = 1u, ///< QSSN hold delay 1.5 QSCK release than QSCK last rising edge
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} en_qspi_qssn_hold_delay_t;
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/**
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*******************************************************************************
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** \brief QSPI address width enumeration
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******************************************************************************/
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typedef enum en_qspi_addr_width
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{
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QspiAddressByteOne = 0u, ///< One byte address
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QspiAddressByteTwo = 1u, ///< Two byte address
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QspiAddressByteThree = 2u, ///< Three byte address
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QspiAddressByteFour = 3u, ///< Four byte address
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} en_qspi_addr_width_t;
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/**
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*******************************************************************************
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** \brief QSPI flag type enumeration
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******************************************************************************/
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typedef enum en_qspi_flag_type
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{
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QspiFlagBusBusy = 0u, ///< QSPI bus work status flag in direct communication mode
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QspiFlagXipMode = 1u, ///< XIP mode status signal
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QspiFlagRomAccessError = 2u, ///< Trigger rom access error flag in direct communication mode
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QspiFlagPrefetchBufferFull = 3u, ///< Prefetch buffer area status signal
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QspiFlagPrefetchStop = 4u, ///< Prefetch action status signal
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} en_qspi_flag_type_t;
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/**
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*******************************************************************************
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** \brief QSPI clock division enumeration
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******************************************************************************/
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typedef enum en_qspi_clk_div
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{
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QspiHclkDiv2 = 0u, ///< Clock source: HCLK/2
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QspiHclkDiv3 = 2u, ///< Clock source: HCLK/3
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QspiHclkDiv4 = 3u, ///< Clock source: HCLK/4
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QspiHclkDiv5 = 4u, ///< Clock source: HCLK/5
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QspiHclkDiv6 = 5u, ///< Clock source: HCLK/6
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QspiHclkDiv7 = 6u, ///< Clock source: HCLK/7
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QspiHclkDiv8 = 7u, ///< Clock source: HCLK/8
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QspiHclkDiv9 = 8u, ///< Clock source: HCLK/9
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QspiHclkDiv10 = 9u, ///< Clock source: HCLK/10
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QspiHclkDiv11 = 10u, ///< Clock source: HCLK/11
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QspiHclkDiv12 = 11u, ///< Clock source: HCLK/12
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QspiHclkDiv13 = 12u, ///< Clock source: HCLK/13
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QspiHclkDiv14 = 13u, ///< Clock source: HCLK/14
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QspiHclkDiv15 = 14u, ///< Clock source: HCLK/15
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QspiHclkDiv16 = 15u, ///< Clock source: HCLK/16
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QspiHclkDiv17 = 16u, ///< Clock source: HCLK/17
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QspiHclkDiv18 = 17u, ///< Clock source: HCLK/18
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QspiHclkDiv19 = 18u, ///< Clock source: HCLK/19
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QspiHclkDiv20 = 19u, ///< Clock source: HCLK/20
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QspiHclkDiv21 = 20u, ///< Clock source: HCLK/21
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QspiHclkDiv22 = 21u, ///< Clock source: HCLK/22
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QspiHclkDiv23 = 22u, ///< Clock source: HCLK/23
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QspiHclkDiv24 = 23u, ///< Clock source: HCLK/24
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QspiHclkDiv25 = 24u, ///< Clock source: HCLK/25
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QspiHclkDiv26 = 25u, ///< Clock source: HCLK/26
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QspiHclkDiv27 = 26u, ///< Clock source: HCLK/27
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QspiHclkDiv28 = 27u, ///< Clock source: HCLK/28
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QspiHclkDiv29 = 28u, ///< Clock source: HCLK/29
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QspiHclkDiv30 = 29u, ///< Clock source: HCLK/30
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QspiHclkDiv31 = 30u, ///< Clock source: HCLK/31
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QspiHclkDiv32 = 31u, ///< Clock source: HCLK/32
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QspiHclkDiv33 = 32u, ///< Clock source: HCLK/33
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QspiHclkDiv34 = 33u, ///< Clock source: HCLK/34
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QspiHclkDiv35 = 34u, ///< Clock source: HCLK/35
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QspiHclkDiv36 = 35u, ///< Clock source: HCLK/36
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QspiHclkDiv37 = 36u, ///< Clock source: HCLK/37
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QspiHclkDiv38 = 37u, ///< Clock source: HCLK/38
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QspiHclkDiv39 = 38u, ///< Clock source: HCLK/39
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QspiHclkDiv40 = 39u, ///< Clock source: HCLK/40
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QspiHclkDiv41 = 40u, ///< Clock source: HCLK/41
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QspiHclkDiv42 = 41u, ///< Clock source: HCLK/42
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QspiHclkDiv43 = 42u, ///< Clock source: HCLK/43
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QspiHclkDiv44 = 43u, ///< Clock source: HCLK/44
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QspiHclkDiv45 = 44u, ///< Clock source: HCLK/45
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QspiHclkDiv46 = 45u, ///< Clock source: HCLK/46
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QspiHclkDiv47 = 46u, ///< Clock source: HCLK/47
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QspiHclkDiv48 = 47u, ///< Clock source: HCLK/48
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QspiHclkDiv49 = 48u, ///< Clock source: HCLK/49
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QspiHclkDiv50 = 49u, ///< Clock source: HCLK/50
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QspiHclkDiv51 = 50u, ///< Clock source: HCLK/51
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QspiHclkDiv52 = 51u, ///< Clock source: HCLK/52
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QspiHclkDiv53 = 52u, ///< Clock source: HCLK/53
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QspiHclkDiv54 = 53u, ///< Clock source: HCLK/54
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QspiHclkDiv55 = 54u, ///< Clock source: HCLK/55
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QspiHclkDiv56 = 55u, ///< Clock source: HCLK/56
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QspiHclkDiv57 = 56u, ///< Clock source: HCLK/57
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QspiHclkDiv58 = 57u, ///< Clock source: HCLK/58
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QspiHclkDiv59 = 58u, ///< Clock source: HCLK/59
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QspiHclkDiv60 = 59u, ///< Clock source: HCLK/60
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QspiHclkDiv61 = 60u, ///< Clock source: HCLK/61
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QspiHclkDiv62 = 61u, ///< Clock source: HCLK/62
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QspiHclkDiv63 = 62u, ///< Clock source: HCLK/63
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QspiHclkDiv64 = 63u, ///< Clock source: HCLK/64
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} en_qspi_clk_div_t;
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/**
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*******************************************************************************
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** \brief QSPI QSSN minimum interval time enumeration
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******************************************************************************/
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typedef enum en_qspi_qssn_interval_time
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{
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QspiQssnIntervalQsck1 = 0u, ///< QSSN signal min interval time 1 QSCK
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QspiQssnIntervalQsck2 = 1u, ///< QSSN signal min interval time 2 QSCK
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QspiQssnIntervalQsck3 = 2u, ///< QSSN signal min interval time 3 QSCK
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QspiQssnIntervalQsck4 = 3u, ///< QSSN signal min interval time 4 QSCK
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QspiQssnIntervalQsck5 = 4u, ///< QSSN signal min interval time 5 QSCK
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QspiQssnIntervalQsck6 = 5u, ///< QSSN signal min interval time 6 QSCK
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QspiQssnIntervalQsck7 = 6u, ///< QSSN signal min interval time 7 QSCK
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QspiQssnIntervalQsck8 = 7u, ///< QSSN signal min interval time 8 QSCK
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QspiQssnIntervalQsck9 = 8u, ///< QSSN signal min interval time 9 QSCK
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QspiQssnIntervalQsck10 = 9u, ///< QSSN signal min interval time 10 QSCK
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QspiQssnIntervalQsck11 = 10u, ///< QSSN signal min interval time 11 QSCK
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QspiQssnIntervalQsck12 = 11u, ///< QSSN signal min interval time 12 QSCK
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QspiQssnIntervalQsck13 = 12u, ///< QSSN signal min interval time 13 QSCK
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QspiQssnIntervalQsck14 = 13u, ///< QSSN signal min interval time 14 QSCK
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QspiQssnIntervalQsck15 = 14u, ///< QSSN signal min interval time 15 QSCK
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QspiQssnIntervalQsck16 = 15u, ///< QSSN signal min interval time 16 QSCK
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} en_qspi_qssn_interval_time_t;
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/**
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*******************************************************************************
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** \brief QSPI virtual period enumeration
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******************************************************************************/
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typedef enum en_qspi_virtual_period
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{
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QspiVirtualPeriodQsck3 = 0u, ///< Virtual period select 3 QSCK
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QspiVirtualPeriodQsck4 = 1u, ///< Virtual period select 4 QSCK
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QspiVirtualPeriodQsck5 = 2u, ///< Virtual period select 5 QSCK
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QspiVirtualPeriodQsck6 = 3u, ///< Virtual period select 6 QSCK
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QspiVirtualPeriodQsck7 = 4u, ///< Virtual period select 7 QSCK
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QspiVirtualPeriodQsck8 = 5u, ///< Virtual period select 8 QSCK
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QspiVirtualPeriodQsck9 = 6u, ///< Virtual period select 9 QSCK
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QspiVirtualPeriodQsck10 = 7u, ///< Virtual period select 10 QSCK
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QspiVirtualPeriodQsck11 = 8u, ///< Virtual period select 11 QSCK
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QspiVirtualPeriodQsck12 = 9u, ///< Virtual period select 12 QSCK
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QspiVirtualPeriodQsck13 = 10u, ///< Virtual period select 13 QSCK
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QspiVirtualPeriodQsck14 = 11u, ///< Virtual period select 14 QSCK
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QspiVirtualPeriodQsck15 = 12u, ///< Virtual period select 15 QSCK
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QspiVirtualPeriodQsck16 = 13u, ///< Virtual period select 16 QSCK
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QspiVirtualPeriodQsck17 = 14u, ///< Virtual period select 17 QSCK
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QspiVirtualPeriodQsck18 = 15u, ///< Virtual period select 18 QSCK
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} en_qspi_virtual_period_t;
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/**
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*******************************************************************************
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** \brief QSPI communication protocol structure definition
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******************************************************************************/
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typedef struct stc_qspi_comm_protocol
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{
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en_qspi_spi_protocol_t enReceProtocol; ///< Receive data stage SPI protocol
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en_qspi_spi_protocol_t enTransAddrProtocol; ///< Transmit address stage SPI protocol
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en_qspi_spi_protocol_t enTransInstrProtocol; ///< Transmit instruction stage SPI protocol
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en_qspi_read_mode_t enReadMode; ///< Serial interface read mode
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} stc_qspi_comm_protocol_t;
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/**
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*******************************************************************************
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** \brief QSPI init structure definition
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******************************************************************************/
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typedef struct stc_qspi_init
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{
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en_qspi_clk_div_t enClkDiv; ///< Clock division
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en_qspi_spi_mode_t enSpiMode; ///< Specifies SPI mode
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en_qspi_bus_mode_t enBusCommMode; ///< Bus communication mode
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en_qspi_prefetch_config_t enPrefetchMode; ///< Config prefetch stop location
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en_functional_state_t enPrefetchFuncEn; ///< Disable: disable prefetch function, Enable: enable prefetch function
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stc_qspi_comm_protocol_t stcCommProtocol; ///< Qspi communication protocol config
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en_qspi_qssn_valid_extend_time_t enQssnValidExtendTime; ///< QSSN valid extend time function select after QSPI access bus
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en_qspi_qssn_interval_time_t enQssnIntervalTime; ///< QSSN minimum interval time
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en_qspi_qsck_duty_correction_t enQsckDutyCorr; ///< QSCK output duty cycles correction
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en_qspi_virtual_period_t enVirtualPeriod; ///< Virtual period config
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en_qspi_wp_pin_level_t enWpPinLevel; ///< WP pin(QIO2) level select
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en_qspi_qssn_setup_delay_t enQssnSetupDelayTime; ///< QSSN setup delay time choose
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en_qspi_qssn_hold_delay_t enQssnHoldDelayTime; ///< QSSN hold delay time choose
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en_functional_state_t enFourByteAddrReadEn; ///< Read instruction code select when set address width is four bytes
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en_qspi_addr_width_t enAddrWidth; ///< Serial interface address width choose
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uint8_t u8RomAccessInstr; ///< Rom access mode instruction
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} stc_qspi_init_t;
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/*!< 4-byte instruction mode using instruction set */
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#define QSPI_4BINSTR_STANDARD_READ 0x13u
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#define QSPI_4BINSTR_FAST_READ 0x0Cu
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#define QSPI_4BINSTR_TWO_WIRES_OUTPUT_READ 0x3Cu
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#define QSPI_4BINSTR_TWO_WIRES_IO_READ 0xBCu
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#define QSPI_4BINSTR_FOUR_WIRES_OUTPUT_READ 0x6Cu
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#define QSPI_4BINSTR_FOUR_WIRES_IO_READ 0xECu
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#define QSPI_4BINSTR_EXIT_4BINSTR_MODE 0xB7u
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/*!< 3-byte instruction mode using instruction set */
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#define QSPI_3BINSTR_STANDARD_READ 0x03u
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#define QSPI_3BINSTR_FAST_READ 0x0Bu
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#define QSPI_3BINSTR_TWO_WIRES_OUTPUT_READ 0x3Bu
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#define QSPI_3BINSTR_TWO_WIRES_IO_READ 0xBBu
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#define QSPI_3BINSTR_FOUR_WIRES_OUTPUT_READ 0x6Bu
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#define QSPI_3BINSTR_FOUR_WIRES_IO_READ 0xEBu
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#define QSPI_3BINSTR_ENTER_4BINSTR_MODE 0xE9u
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/*!< General instruction set */
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#define QSPI_WRITE_MODE_ENABLE 0x06u
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/* Base functions */
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en_result_t QSPI_DeInit(void);
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en_result_t QSPI_Init(const stc_qspi_init_t *pstcQspiInitCfg);
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en_result_t QSPI_SetAddrWidth(en_qspi_addr_width_t enAddrWidth);
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en_result_t QSPI_SetExtendAddress(uint8_t u8Addr);
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en_result_t QSPI_CommProtocolConfig(const stc_qspi_comm_protocol_t *pstcCommProtocol);
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en_result_t QSPI_PrefetchCmd(en_functional_state_t enNewSta);
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en_result_t QSPI_SetClockDiv(en_qspi_clk_div_t enClkDiv);
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en_result_t QSPI_SetWPPinLevel(en_qspi_wp_pin_level_t enWpLevel);
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/* Rom access mode functions */
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en_result_t QSPI_SetRomAccessInstruct(uint8_t u8Instr);
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en_result_t QSPI_XipModeCmd(uint8_t u8Instr, en_functional_state_t enNewSta);
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/* Direct communication mode functions */
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en_result_t QSPI_WriteDirectCommValue(uint8_t u8Val);
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uint8_t QSPI_ReadDirectCommValue(void);
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en_result_t QSPI_EnterDirectCommMode(void);
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en_result_t QSPI_ExitDirectCommMode(void);
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/* Flags and get buffer functions */
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uint8_t QSPI_GetPrefetchBufferNum(void);
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en_flag_status_t QSPI_GetFlag(en_qspi_flag_type_t enFlag);
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en_result_t QSPI_ClearFlag(en_qspi_flag_type_t enFlag);
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//@} // QspiGroup
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#ifdef __cplusplus
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}
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#endif
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#endif /* DDL_QSPI_ENABLE */
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#endif /* __HC32F460_QSPI_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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