65 lines
1.1 KiB
C
65 lines
1.1 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-10-03 Bernard The first version
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*/
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#ifndef CPUPORT_H__
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#define CPUPORT_H__
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#include <rtconfig.h>
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#include <opcode.h>
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/* bytes of register width */
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#ifdef ARCH_CPU_64BIT
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#define STORE sd
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#define LOAD ld
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#define REGBYTES 8
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#else
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// error here, not portable
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#endif
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/* 33 general register */
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#define CTX_GENERAL_REG_NR 33
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#ifdef ENABLE_FPU
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/* 32 fpu register */
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#define CTX_FPU_REG_NR 32
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#else
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#define CTX_FPU_REG_NR 0
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#endif
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/* all context registers */
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#define CTX_REG_NR (CTX_GENERAL_REG_NR + CTX_FPU_REG_NR)
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#ifndef __ASSEMBLY__
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#include <rtdef.h>
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rt_inline void rt_hw_dsb(void)
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{
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__asm__ volatile("fence":::"memory");
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}
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rt_inline void rt_hw_dmb(void)
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{
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__asm__ volatile("fence":::"memory");
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}
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rt_inline void rt_hw_isb(void)
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{
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__asm__ volatile(OPC_FENCE_I:::"memory");
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}
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int rt_hw_cpu_id(void);
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#endif
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#endif
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#ifdef RISCV_U_MODE
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#define RISCV_USER_ENTRY 0xFFFFFFE000000000ULL
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#endif
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