55c9827096
* Add SAML10 Cortex-M23 series support 1. Add SAML10 Cortex-M23 series support; 2. remove STDIO related code of same54 series, no need any more; 3. update rtconfig.py to support output bin & map file containing DEVICE PART info.
67 lines
2.9 KiB
C
67 lines
2.9 KiB
C
/**
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* \file
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*
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* \brief Instance description for MCLK
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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/* file generated from device description version 2019-01-31T14:29:25Z */
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#ifndef _SAML10_MCLK_INSTANCE_H_
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#define _SAML10_MCLK_INSTANCE_H_
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/* ========== Register definition for MCLK peripheral ========== */
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#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_MCLK_CTRLA (0x40000800) /**< (MCLK) Control */
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#define REG_MCLK_INTENCLR (0x40000801) /**< (MCLK) Interrupt Enable Clear */
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#define REG_MCLK_INTENSET (0x40000802) /**< (MCLK) Interrupt Enable Set */
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#define REG_MCLK_INTFLAG (0x40000803) /**< (MCLK) Interrupt Flag Status and Clear */
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#define REG_MCLK_CPUDIV (0x40000804) /**< (MCLK) CPU Clock Division */
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#define REG_MCLK_AHBMASK (0x40000810) /**< (MCLK) AHB Mask */
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#define REG_MCLK_APBAMASK (0x40000814) /**< (MCLK) APBA Mask */
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#define REG_MCLK_APBBMASK (0x40000818) /**< (MCLK) APBB Mask */
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#define REG_MCLK_APBCMASK (0x4000081C) /**< (MCLK) APBC Mask */
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#else
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#define REG_MCLK_CTRLA (*(__IO uint8_t*)0x40000800U) /**< (MCLK) Control */
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#define REG_MCLK_INTENCLR (*(__IO uint8_t*)0x40000801U) /**< (MCLK) Interrupt Enable Clear */
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#define REG_MCLK_INTENSET (*(__IO uint8_t*)0x40000802U) /**< (MCLK) Interrupt Enable Set */
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#define REG_MCLK_INTFLAG (*(__IO uint8_t*)0x40000803U) /**< (MCLK) Interrupt Flag Status and Clear */
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#define REG_MCLK_CPUDIV (*(__IO uint8_t*)0x40000804U) /**< (MCLK) CPU Clock Division */
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#define REG_MCLK_AHBMASK (*(__IO uint32_t*)0x40000810U) /**< (MCLK) AHB Mask */
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#define REG_MCLK_APBAMASK (*(__IO uint32_t*)0x40000814U) /**< (MCLK) APBA Mask */
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#define REG_MCLK_APBBMASK (*(__IO uint32_t*)0x40000818U) /**< (MCLK) APBB Mask */
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#define REG_MCLK_APBCMASK (*(__IO uint32_t*)0x4000081CU) /**< (MCLK) APBC Mask */
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#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance Parameter definitions for MCLK peripheral ========== */
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#define MCLK_MCLK_CLK_APB_NUM 3
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#define MCLK_SYSTEM_CLOCK 4000000 /* System Clock Frequency at Reset */
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#define MCLK_INSTANCE_ID 2
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#endif /* _SAML10_MCLK_INSTANCE_ */
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