55c9827096
* Add SAML10 Cortex-M23 series support 1. Add SAML10 Cortex-M23 series support; 2. remove STDIO related code of same54 series, no need any more; 3. update rtconfig.py to support output bin & map file containing DEVICE PART info.
85 lines
4.8 KiB
C
85 lines
4.8 KiB
C
/**
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* \file
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*
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* \brief Instance description for EIC
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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/* file generated from device description version 2019-01-31T14:29:25Z */
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#ifndef _SAML10_EIC_INSTANCE_H_
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#define _SAML10_EIC_INSTANCE_H_
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/* ========== Register definition for EIC peripheral ========== */
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#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_EIC_CTRLA (0x40002800) /**< (EIC) Control A */
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#define REG_EIC_NMICTRL (0x40002801) /**< (EIC) Non-Maskable Interrupt Control */
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#define REG_EIC_NMIFLAG (0x40002802) /**< (EIC) Non-Maskable Interrupt Flag Status and Clear */
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#define REG_EIC_SYNCBUSY (0x40002804) /**< (EIC) Synchronization Busy */
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#define REG_EIC_EVCTRL (0x40002808) /**< (EIC) Event Control */
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#define REG_EIC_INTENCLR (0x4000280C) /**< (EIC) Interrupt Enable Clear */
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#define REG_EIC_INTENSET (0x40002810) /**< (EIC) Interrupt Enable Set */
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#define REG_EIC_INTFLAG (0x40002814) /**< (EIC) Interrupt Flag Status and Clear */
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#define REG_EIC_ASYNCH (0x40002818) /**< (EIC) External Interrupt Asynchronous Mode */
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#define REG_EIC_CONFIG (0x4000281C) /**< (EIC) External Interrupt Sense Configuration */
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#define REG_EIC_CONFIG0 (0x4000281C) /**< (EIC) External Interrupt Sense Configuration 0 */
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#define REG_EIC_DEBOUNCEN (0x40002830) /**< (EIC) Debouncer Enable */
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#define REG_EIC_DPRESCALER (0x40002834) /**< (EIC) Debouncer Prescaler */
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#define REG_EIC_PINSTATE (0x40002838) /**< (EIC) Pin State */
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#define REG_EIC_NSCHK (0x4000283C) /**< (EIC) Non-secure Interrupt Check Enable */
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#define REG_EIC_NONSEC (0x40002840) /**< (EIC) Non-secure Interrupt */
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#else
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#define REG_EIC_CTRLA (*(__IO uint8_t*)0x40002800U) /**< (EIC) Control A */
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#define REG_EIC_NMICTRL (*(__IO uint8_t*)0x40002801U) /**< (EIC) Non-Maskable Interrupt Control */
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#define REG_EIC_NMIFLAG (*(__IO uint8_t*)0x40002802U) /**< (EIC) Non-Maskable Interrupt Flag Status and Clear */
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#define REG_EIC_SYNCBUSY (*(__I uint32_t*)0x40002804U) /**< (EIC) Synchronization Busy */
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#define REG_EIC_EVCTRL (*(__IO uint32_t*)0x40002808U) /**< (EIC) Event Control */
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#define REG_EIC_INTENCLR (*(__IO uint32_t*)0x4000280CU) /**< (EIC) Interrupt Enable Clear */
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#define REG_EIC_INTENSET (*(__IO uint32_t*)0x40002810U) /**< (EIC) Interrupt Enable Set */
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#define REG_EIC_INTFLAG (*(__IO uint32_t*)0x40002814U) /**< (EIC) Interrupt Flag Status and Clear */
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#define REG_EIC_ASYNCH (*(__IO uint32_t*)0x40002818U) /**< (EIC) External Interrupt Asynchronous Mode */
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#define REG_EIC_CONFIG (*(__IO uint32_t*)0x4000281CU) /**< (EIC) External Interrupt Sense Configuration */
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#define REG_EIC_CONFIG0 (*(__IO uint32_t*)0x4000281CU) /**< (EIC) External Interrupt Sense Configuration 0 */
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#define REG_EIC_DEBOUNCEN (*(__IO uint32_t*)0x40002830U) /**< (EIC) Debouncer Enable */
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#define REG_EIC_DPRESCALER (*(__IO uint32_t*)0x40002834U) /**< (EIC) Debouncer Prescaler */
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#define REG_EIC_PINSTATE (*(__I uint32_t*)0x40002838U) /**< (EIC) Pin State */
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#define REG_EIC_NSCHK (*(__IO uint32_t*)0x4000283CU) /**< (EIC) Non-secure Interrupt Check Enable */
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#define REG_EIC_NONSEC (*(__IO uint32_t*)0x40002840U) /**< (EIC) Non-secure Interrupt */
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#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance Parameter definitions for EIC peripheral ========== */
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#define EIC_EXTINT_NUM 8 /* Number of external interrupts */
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#define EIC_GCLK_ID 3 /* Generic Clock index */
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#define EIC_NUMBER_OF_CONFIG_REGS 1 /* Number of CONFIG registers */
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#define EIC_NUMBER_OF_DPRESCALER_REGS 1 /* Number of DPRESCALER registers */
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#define EIC_NUMBER_OF_INTERRUPTS 8 /* Number of external interrupts (obsolete) */
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#define EIC_SECURE_IMPLEMENTED 1 /* Security Configuration implemented? */
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#define EIC_INSTANCE_ID 10
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#endif /* _SAML10_EIC_INSTANCE_ */
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