55c9827096
* Add SAML10 Cortex-M23 series support 1. Add SAML10 Cortex-M23 series support; 2. remove STDIO related code of same54 series, no need any more; 3. update rtconfig.py to support output bin & map file containing DEVICE PART info.
104 lines
3.1 KiB
C
104 lines
3.1 KiB
C
/**
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* \file
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*
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* \brief SAM RSTC
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*
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* Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifdef _SAML10_RSTC_COMPONENT_
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#ifndef _HRI_RSTC_L10_H_INCLUDED_
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#define _HRI_RSTC_L10_H_INCLUDED_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include <hal_atomic.h>
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#if defined(ENABLE_RSTC_CRITICAL_SECTIONS)
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#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
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#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
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#else
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#define RSTC_CRITICAL_SECTION_ENTER()
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#define RSTC_CRITICAL_SECTION_LEAVE()
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#endif
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typedef uint8_t hri_rstc_rcause_reg_t;
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static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw)
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{
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return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR_Msk) >> RSTC_RCAUSE_POR_Pos;
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}
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static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw)
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{
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return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE_Msk) >> RSTC_RCAUSE_BODCORE_Pos;
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}
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static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw)
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{
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return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD_Msk) >> RSTC_RCAUSE_BODVDD_Pos;
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}
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static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw)
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{
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return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT_Msk) >> RSTC_RCAUSE_EXT_Pos;
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}
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static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw)
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{
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return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT_Msk) >> RSTC_RCAUSE_WDT_Pos;
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}
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static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw)
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{
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return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST_Msk) >> RSTC_RCAUSE_SYST_Pos;
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}
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static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask)
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{
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uint8_t tmp;
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tmp = ((Rstc *)hw)->RCAUSE.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw)
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{
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return ((Rstc *)hw)->RCAUSE.reg;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HRI_RSTC_L10_H_INCLUDED */
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#endif /* _SAML10_RSTC_COMPONENT_ */
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