591 lines
20 KiB
Plaintext
591 lines
20 KiB
Plaintext
format_version: '2'
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name: SAML10 LED switcher
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versions:
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api: '1.0'
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backend: 1.8.580
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commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c
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content: unknown
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content_pack_name: unknown
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format: '2'
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frontend: 1.8.580
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packs_version_avr8: 1.0.1463
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packs_version_qtouch: unknown
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packs_version_sam: 1.0.1726
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version_backend: 1.8.580
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version_frontend: ''
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board:
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identifier: SAML10XplainedPro
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device: ATSAML10E16A-AU
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details: null
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application:
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definition: 'Atmel:Application_Examples:0.0.1::Application:EDBG_UART:'
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configuration: {}
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middlewares: {}
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drivers:
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ADC_0:
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user_label: ADC_0
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definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::ADC::driver_config_definition::ADC::HAL:Driver:ADC.Sync
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functionality: ADC
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api: HAL:Driver:ADC_Sync
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configuration:
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adc_advanced_settings: true
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adc_arch_adjres: 0
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adc_arch_corren: false
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adc_arch_dbgrun: false
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adc_arch_event_settings: false
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adc_arch_flushei: false
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adc_arch_flushinv: false
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adc_arch_gaincorr: 0
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adc_arch_leftadj: false
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adc_arch_offcomp: false
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adc_arch_offsetcorr: 0
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adc_arch_ondemand: false
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adc_arch_refcomp: false
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adc_arch_resrdyeo: false
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adc_arch_runstdby: false
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adc_arch_samplen: 0
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adc_arch_samplenum: 4 samples
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adc_arch_seqen: 0
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adc_arch_startei: false
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adc_arch_startinv: false
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adc_arch_winlt: 0
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adc_arch_winmode: No window mode
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adc_arch_winmoneo: false
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adc_arch_winut: 0
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adc_differential_mode: false
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adc_freerunning_mode: false
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adc_pinmux_negative: Internal ground
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adc_pinmux_positive: ADC AIN0 pin
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adc_prescaler: Peripheral clock divided by 2
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adc_reference: VDDANA
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adc_resolution: 12-bit
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optional_signals:
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- identifier: ADC_0:AIN/0
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pad: PA02
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mode: Enabled
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configuration: null
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definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::optional_signal_definition::ADC.AIN.0
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name: ADC/AIN/0
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label: AIN/0
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variant: null
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clocks:
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domain_group:
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nodes:
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- name: ADC
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input: Generic clock generator 0
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external: false
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external_frequency: 0
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configuration:
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adc_gclk_selection: Generic clock generator 0
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DMAC:
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user_label: DMAC
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definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
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functionality: System
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api: HAL:HPL:DMAC
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configuration:
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dmac_beatsize_0: 8-bit bus transfer
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dmac_beatsize_1: 8-bit bus transfer
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dmac_beatsize_2: 8-bit bus transfer
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dmac_beatsize_3: 8-bit bus transfer
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dmac_beatsize_4: 8-bit bus transfer
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dmac_beatsize_5: 8-bit bus transfer
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dmac_beatsize_6: 8-bit bus transfer
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dmac_beatsize_7: 8-bit bus transfer
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dmac_blockact_0: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_1: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_2: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_3: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_4: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_5: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_6: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_blockact_7: Channel will be disabled if it is the last block transfer in
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the transaction
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dmac_channel_0_settings: false
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dmac_channel_1_settings: false
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dmac_channel_2_settings: false
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dmac_channel_3_settings: false
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dmac_channel_4_settings: false
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dmac_channel_5_settings: false
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dmac_channel_6_settings: false
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dmac_channel_7_settings: false
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dmac_dbgrun: false
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dmac_dqos: Background (no sensitive operation)
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dmac_dstinc_0: false
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dmac_dstinc_1: false
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dmac_dstinc_2: false
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dmac_dstinc_3: false
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dmac_dstinc_4: false
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dmac_dstinc_5: false
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dmac_dstinc_6: false
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dmac_dstinc_7: false
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dmac_enable: false
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dmac_enable_0: false
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dmac_enable_1: false
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dmac_enable_2: false
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dmac_enable_3: false
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dmac_enable_4: false
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dmac_enable_5: false
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dmac_enable_6: false
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dmac_enable_7: false
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dmac_evact_0: No action
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dmac_evact_1: No action
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dmac_evact_2: No action
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dmac_evact_3: No action
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dmac_evact_4: No action
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dmac_evact_5: No action
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dmac_evact_6: No action
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dmac_evact_7: No action
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dmac_evie_0: false
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dmac_evie_1: false
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dmac_evie_2: false
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dmac_evie_3: false
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dmac_evie_4: false
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dmac_evie_5: false
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dmac_evie_6: false
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dmac_evie_7: false
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dmac_evoe_0: false
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dmac_evoe_1: false
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dmac_evoe_2: false
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dmac_evoe_3: false
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dmac_evoe_4: false
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dmac_evoe_5: false
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dmac_evoe_6: false
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dmac_evoe_7: false
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dmac_evosel_0: Event generation disabled
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dmac_evosel_1: Event generation disabled
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dmac_evosel_2: Event generation disabled
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dmac_evosel_3: Event generation disabled
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dmac_evosel_4: Event generation disabled
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dmac_evosel_5: Event generation disabled
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dmac_evosel_6: Event generation disabled
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dmac_evosel_7: Event generation disabled
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dmac_fqos: Background (no sensitive operation)
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dmac_lvl_0: Channel priority 0
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dmac_lvl_1: Channel priority 0
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dmac_lvl_2: Channel priority 0
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dmac_lvl_3: Channel priority 0
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dmac_lvl_4: Channel priority 0
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dmac_lvl_5: Channel priority 0
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dmac_lvl_6: Channel priority 0
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dmac_lvl_7: Channel priority 0
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dmac_lvlen0: false
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dmac_lvlen1: false
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dmac_lvlen2: false
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dmac_lvlen3: false
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dmac_lvlpri0: 0
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dmac_lvlpri1: 0
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dmac_lvlpri2: 0
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dmac_lvlpri3: 0
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dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
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dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
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dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
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dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
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dmac_runstdby_0: false
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dmac_runstdby_1: false
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dmac_runstdby_2: false
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dmac_runstdby_3: false
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dmac_runstdby_4: false
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dmac_runstdby_5: false
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dmac_runstdby_6: false
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dmac_runstdby_7: false
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dmac_srcinc_0: false
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dmac_srcinc_1: false
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dmac_srcinc_2: false
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dmac_srcinc_3: false
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dmac_srcinc_4: false
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dmac_srcinc_5: false
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dmac_srcinc_6: false
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dmac_srcinc_7: false
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dmac_stepsel_0: Step size settings apply to the destination address
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dmac_stepsel_1: Step size settings apply to the destination address
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dmac_stepsel_2: Step size settings apply to the destination address
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dmac_stepsel_3: Step size settings apply to the destination address
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dmac_stepsel_4: Step size settings apply to the destination address
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dmac_stepsel_5: Step size settings apply to the destination address
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dmac_stepsel_6: Step size settings apply to the destination address
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dmac_stepsel_7: Step size settings apply to the destination address
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dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
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dmac_trifsrc_0: Only software/event triggers
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dmac_trifsrc_1: Only software/event triggers
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dmac_trifsrc_2: Only software/event triggers
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dmac_trifsrc_3: Only software/event triggers
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dmac_trifsrc_4: Only software/event triggers
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dmac_trifsrc_5: Only software/event triggers
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dmac_trifsrc_6: Only software/event triggers
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dmac_trifsrc_7: Only software/event triggers
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dmac_trigact_0: One trigger required for each block transfer
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dmac_trigact_1: One trigger required for each block transfer
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dmac_trigact_2: One trigger required for each block transfer
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dmac_trigact_3: One trigger required for each block transfer
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dmac_trigact_4: One trigger required for each block transfer
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dmac_trigact_5: One trigger required for each block transfer
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dmac_trigact_6: One trigger required for each block transfer
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dmac_trigact_7: One trigger required for each block transfer
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dmac_wrbqos: Background (no sensitive operation)
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optional_signals: []
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variant: null
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clocks:
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domain_group: null
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GCLK:
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user_label: GCLK
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definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
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functionality: System
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api: HAL:HPL:GCLK
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configuration:
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$input: 32000000
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$input_id: Digital Phase Locked Loop (DPLL)
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RESERVED_InputFreq: 32000000
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RESERVED_InputFreq_id: Digital Phase Locked Loop (DPLL)
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_$freq_output_Generic clock generator 0: 32000000
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_$freq_output_Generic clock generator 1: 32768
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_$freq_output_Generic clock generator 2: 400000
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_$freq_output_Generic clock generator 3: 32768
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_$freq_output_Generic clock generator 4: 400000
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enable_gclk_gen_0: true
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enable_gclk_gen_0__externalclock: 1000000
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enable_gclk_gen_1: true
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enable_gclk_gen_1__externalclock: 1000000
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enable_gclk_gen_2: false
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enable_gclk_gen_2__externalclock: 1000000
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enable_gclk_gen_3: false
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enable_gclk_gen_3__externalclock: 1000000
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enable_gclk_gen_4: false
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enable_gclk_gen_4__externalclock: 1000000
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gclk_arch_gen_0_enable: true
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gclk_arch_gen_0_idc: true
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gclk_arch_gen_0_oe: false
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gclk_arch_gen_0_oov: false
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gclk_arch_gen_0_runstdby: false
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gclk_arch_gen_1_enable: true
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gclk_arch_gen_1_idc: true
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gclk_arch_gen_1_oe: false
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gclk_arch_gen_1_oov: false
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gclk_arch_gen_1_runstdby: false
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gclk_arch_gen_2_enable: false
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gclk_arch_gen_2_idc: false
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gclk_arch_gen_2_oe: false
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gclk_arch_gen_2_oov: false
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gclk_arch_gen_2_runstdby: false
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gclk_arch_gen_3_enable: false
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gclk_arch_gen_3_idc: false
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gclk_arch_gen_3_oe: false
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gclk_arch_gen_3_oov: false
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gclk_arch_gen_3_runstdby: false
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gclk_arch_gen_4_enable: false
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gclk_arch_gen_4_idc: false
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gclk_arch_gen_4_oe: false
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gclk_arch_gen_4_oov: false
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gclk_arch_gen_4_runstdby: false
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gclk_gen_0_div: 1
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gclk_gen_0_div_sel: false
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gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL)
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gclk_gen_1_div: 1
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gclk_gen_1_div_sel: false
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gclk_gen_1_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
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gclk_gen_2_div: 1
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gclk_gen_2_div_sel: false
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gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
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gclk_gen_3_div: 1
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gclk_gen_3_div_sel: false
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gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
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gclk_gen_4_div: 1
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gclk_gen_4_div_sel: false
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gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
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optional_signals: []
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variant: null
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clocks:
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domain_group: null
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MCLK:
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user_label: MCLK
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definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK
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functionality: System
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api: HAL:HPL:MCLK
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configuration:
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$input: 32000000
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$input_id: Generic clock generator 0
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RESERVED_InputFreq: 32000000
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RESERVED_InputFreq_id: Generic clock generator 0
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_$freq_output_CPU: 32000000
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cpu_clock_source: Generic clock generator 0
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cpu_div: '1'
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enable_cpu_clock: true
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nvm_wait_states: '3'
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performance_level: Performance Level 0 (PL0)
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optional_signals: []
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variant: null
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clocks:
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domain_group:
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nodes:
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- name: CPU
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input: CPU
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external: false
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external_frequency: 0
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configuration: {}
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OSC32KCTRL:
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user_label: OSC32KCTRL
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definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL
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functionality: System
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api: HAL:HPL:OSC32KCTRL
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configuration:
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$input: 32768
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$input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
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RESERVED_InputFreq: 32768
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RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
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_$freq_output_RTC source: 1024
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enable_osculp32k: true
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enable_rtc_source: false
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enable_xosc32k: true
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osculp32k_arch_ulp32ksw: false
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osculp32k_calib: 0
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osculp32k_calib_enable: false
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rtc_1khz_selection: true
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rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
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xosc32k_arch_cfden: false
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xosc32k_arch_cfdeo: false
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xosc32k_arch_en1k: false
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xosc32k_arch_en32k: false
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xosc32k_arch_enable: true
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xosc32k_arch_ondemand: false
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xosc32k_arch_runstdby: false
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xosc32k_arch_startup: 125092us
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xosc32k_arch_swben: false
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xosc32k_arch_xtalen: true
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optional_signals: []
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variant: null
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clocks:
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domain_group: null
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OSCCTRL:
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user_label: OSCCTRL
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definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL
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functionality: System
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api: HAL:HPL:OSCCTRL
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configuration:
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$input: 32768
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$input_id: Generic clock generator 1
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RESERVED_InputFreq: 32768
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RESERVED_InputFreq_id: Generic clock generator 1
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_$freq_output_16MHz Internal Oscillator (OSC16M): 4000000
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_$freq_output_DFLLULP clock: 4194304
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_$freq_output_Digital Frequency Locked Loop (DFLLULP): 4194304
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_$freq_output_Digital Phase Locked Loop (DPLL): 32000000
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_$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000
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dfllulp_arch_binse: false
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dfllulp_arch_delay: 128
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dfllulp_arch_dither: false
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dfllulp_arch_dither_per: Dither over 1 reference clock period
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dfllulp_arch_dither_step: Dither step is 1
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dfllulp_arch_enable: true
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dfllulp_arch_ondemand: true
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dfllulp_arch_ratio: 128
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dfllulp_arch_runstdby: false
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dfllulp_arch_safe: false
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dfllulp_mode: Closed Loop Mode
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dfllulp_ref_clock: Generic clock generator 1
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dfllulp_source_oscillator: Digital Frequency Locked Loop (DFLLULP)
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enable_dfllulp: true
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enable_dfllulp_as_mclk_source: false
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enable_fdpll96m: true
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enable_osc16m: true
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enable_xosc: false
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fdpll96m_arch_enable: true
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fdpll96m_arch_filter: Default filter mode
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fdpll96m_arch_lbypass: false
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fdpll96m_arch_lpen: false
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fdpll96m_arch_ltime: No time-out, automatic lock
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fdpll96m_arch_ondemand: true
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fdpll96m_arch_refclk: XOSC32K clock reference
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fdpll96m_arch_runstdby: false
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fdpll96m_arch_wuf: false
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fdpll96m_clock_div: 0
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fdpll96m_ldr: 975
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fdpll96m_ldrfrac: 9
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fdpll96m_presc: '1'
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fdpll96m_ref_clock: Generic clock generator 1
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osc16m_arch_enable: true
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osc16m_arch_ondemand: true
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osc16m_arch_runstdby: false
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osc16m_freq: '4'
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xosc_arch_ampgc: false
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xosc_arch_cfden: false
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xosc_arch_cfdeo: false
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xosc_arch_enable: false
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xosc_arch_gain: 2MHz
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xosc_arch_ondemand: true
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xosc_arch_runstdby: false
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xosc_arch_startup: 31us
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xosc_arch_swben: false
|
|
xosc_arch_xtalen: false
|
|
xosc_frequency: 400000
|
|
optional_signals: []
|
|
variant: null
|
|
clocks:
|
|
domain_group: null
|
|
PORT:
|
|
user_label: PORT
|
|
definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT
|
|
functionality: System
|
|
api: HAL:HPL:PORT
|
|
configuration:
|
|
enable_port_input_event_0: false
|
|
enable_port_input_event_1: false
|
|
enable_port_input_event_2: false
|
|
enable_port_input_event_3: false
|
|
porta_event_action_0: Output register of pin will be set to level of event
|
|
porta_event_action_1: Output register of pin will be set to level of event
|
|
porta_event_action_2: Output register of pin will be set to level of event
|
|
porta_event_action_3: Output register of pin will be set to level of event
|
|
porta_event_pin_identifier_0: 0
|
|
porta_event_pin_identifier_1: 0
|
|
porta_event_pin_identifier_2: 0
|
|
porta_event_pin_identifier_3: 0
|
|
porta_input_event_enable_0: false
|
|
porta_input_event_enable_1: false
|
|
porta_input_event_enable_2: false
|
|
porta_input_event_enable_3: false
|
|
optional_signals: []
|
|
variant: null
|
|
clocks:
|
|
domain_group: null
|
|
I2C_0:
|
|
user_label: I2C_0
|
|
definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::SERCOM0::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync
|
|
functionality: I2C
|
|
api: HAL:Driver:I2C_Master_Sync
|
|
configuration:
|
|
i2c_master_advanced: true
|
|
i2c_master_arch_dbgstop: Keep running
|
|
i2c_master_arch_inactout: 20-21 SCL cycle time-out(200-210us)
|
|
i2c_master_arch_lowtout: true
|
|
i2c_master_arch_mexttoen: true
|
|
i2c_master_arch_runstdby: false
|
|
i2c_master_arch_sdahold: 400-800ns hold time
|
|
i2c_master_arch_sexttoen: false
|
|
i2c_master_arch_trise: 215
|
|
i2c_master_baud_rate: 100000
|
|
optional_signals: []
|
|
variant:
|
|
specification: SDA=0, SCL=1
|
|
required_signals:
|
|
- name: SERCOM0/PAD/0
|
|
pad: PA16
|
|
label: SDA
|
|
- name: SERCOM0/PAD/1
|
|
pad: PA17
|
|
label: SCL
|
|
clocks:
|
|
domain_group:
|
|
nodes:
|
|
- name: Core
|
|
input: Generic clock generator 0
|
|
external: false
|
|
external_frequency: 0
|
|
- name: Slow
|
|
input: Generic clock generator 1
|
|
external: false
|
|
external_frequency: 0
|
|
configuration:
|
|
core_gclk_selection: Generic clock generator 0
|
|
slow_gclk_selection: Generic clock generator 1
|
|
TARGET_IO:
|
|
user_label: TARGET_IO
|
|
definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Async
|
|
functionality: USART
|
|
api: HAL:Driver:USART_Async
|
|
configuration:
|
|
usart_advanced: true
|
|
usart_arch_clock_mode: USART with internal clock
|
|
usart_arch_cloden: false
|
|
usart_arch_dbgstop: Keep running
|
|
usart_arch_dord: LSB is transmitted first
|
|
usart_arch_enc: No encoding
|
|
usart_arch_fractional: 0
|
|
usart_arch_ibon: false
|
|
usart_arch_lin_slave_enable: Disable
|
|
usart_arch_runstdby: false
|
|
usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling)
|
|
usart_arch_sampr: 16x arithmetic
|
|
usart_arch_sfde: false
|
|
usart_baud_rate: 115200
|
|
usart_character_size: 8 bits
|
|
usart_parity: No parity
|
|
usart_rx_enable: true
|
|
usart_stop_bit: One stop bit
|
|
usart_tx_enable: true
|
|
optional_signals: []
|
|
variant:
|
|
specification: TXPO=1, RXPO=3, CMODE=0
|
|
required_signals:
|
|
- name: SERCOM2/PAD/2
|
|
pad: PA24
|
|
label: TX
|
|
- name: SERCOM2/PAD/3
|
|
pad: PA25
|
|
label: RX
|
|
clocks:
|
|
domain_group:
|
|
nodes:
|
|
- name: Core
|
|
input: Generic clock generator 0
|
|
external: false
|
|
external_frequency: 0
|
|
- name: Slow
|
|
input: Generic clock generator 1
|
|
external: false
|
|
external_frequency: 0
|
|
configuration:
|
|
core_gclk_selection: Generic clock generator 0
|
|
slow_gclk_selection: Generic clock generator 1
|
|
pads:
|
|
PA02:
|
|
name: PA02
|
|
definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::pad::PA02
|
|
mode: Analog
|
|
user_label: PA02
|
|
configuration: null
|
|
LED0:
|
|
name: PA07
|
|
definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::pad::PA07
|
|
mode: Digital output
|
|
user_label: LED0
|
|
configuration: null
|
|
PA16:
|
|
name: PA16
|
|
definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::pad::PA16
|
|
mode: I2C
|
|
user_label: PA16
|
|
configuration: null
|
|
PA17:
|
|
name: PA17
|
|
definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::pad::PA17
|
|
mode: I2C
|
|
user_label: PA17
|
|
configuration: null
|
|
EDBG_COM_TX:
|
|
name: PA24
|
|
definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::pad::PA24
|
|
mode: Peripheral IO
|
|
user_label: EDBG_COM_TX
|
|
configuration: null
|
|
EDBG_COM_RX:
|
|
name: PA25
|
|
definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::pad::PA25
|
|
mode: Peripheral IO
|
|
user_label: EDBG_COM_RX
|
|
configuration: null
|
|
toolchain_options: []
|
|
static_files: []
|