674 lines
16 KiB
C
674 lines
16 KiB
C
#include <rtthread.h>
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#include <netif/ethernetif.h>
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#include "dm9000.h"
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#include <s3c24x0.h>
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/*
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* Davicom DM9000EP driver
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*
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* IRQ_LAN connects to EINT7(GPF7)
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* nLAN_CS connects to nGCS4
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*/
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/* #define DM9000_DEBUG 1 */
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#if DM9000_DEBUG
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#define DM9000_TRACE rt_kprintf
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#else
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#define DM9000_TRACE(...)
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#endif
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/*
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* DM9000 interrupt line is connected to PF7
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*/
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//--------------------------------------------------------
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#define DM9000_PHY 0x40 /* PHY address 0x01 */
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#define MAX_ADDR_LEN 6
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enum DM9000_PHY_mode
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{
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DM9000_10MHD = 0, DM9000_100MHD = 1,
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DM9000_10MFD = 4, DM9000_100MFD = 5,
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DM9000_AUTO = 8, DM9000_1M_HPNA = 0x10
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};
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enum DM9000_TYPE
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{
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TYPE_DM9000E,
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TYPE_DM9000A,
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TYPE_DM9000B
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};
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struct rt_dm9000_eth
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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enum DM9000_TYPE type;
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enum DM9000_PHY_mode mode;
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rt_uint8_t packet_cnt; /* packet I or II */
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rt_uint16_t queue_packet_len; /* queued packet (packet II) */
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/* interface address info. */
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rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
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};
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static struct rt_dm9000_eth dm9000_device;
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static struct rt_semaphore sem_ack, sem_lock;
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void rt_dm9000_isr(int irqno);
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static void delay_ms(rt_uint32_t ms)
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{
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rt_uint32_t len;
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for (;ms > 0; ms --)
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for (len = 0; len < 100; len++ );
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}
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/* Read a byte from I/O port */
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rt_inline rt_uint8_t dm9000_io_read(rt_uint16_t reg)
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{
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DM9000_IO = reg;
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return (rt_uint8_t) DM9000_DATA;
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}
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/* Write a byte to I/O port */
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rt_inline void dm9000_io_write(rt_uint16_t reg, rt_uint16_t value)
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{
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DM9000_IO = reg;
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DM9000_DATA = value;
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}
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/* Read a word from phyxcer */
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rt_inline rt_uint16_t phy_read(rt_uint16_t reg)
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{
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rt_uint16_t val;
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/* Fill the phyxcer register into REG_0C */
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dm9000_io_write(DM9000_EPAR, DM9000_PHY | reg);
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dm9000_io_write(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
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delay_ms(100); /* Wait read complete */
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dm9000_io_write(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
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val = (dm9000_io_read(DM9000_EPDRH) << 8) | dm9000_io_read(DM9000_EPDRL);
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return val;
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}
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/* Write a word to phyxcer */
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rt_inline void phy_write(rt_uint16_t reg, rt_uint16_t value)
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{
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/* Fill the phyxcer register into REG_0C */
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dm9000_io_write(DM9000_EPAR, DM9000_PHY | reg);
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/* Fill the written data into REG_0D & REG_0E */
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dm9000_io_write(DM9000_EPDRL, (value & 0xff));
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dm9000_io_write(DM9000_EPDRH, ((value >> 8) & 0xff));
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dm9000_io_write(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
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delay_ms(500); /* Wait write complete */
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dm9000_io_write(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
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}
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/* Set PHY operationg mode */
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rt_inline void phy_mode_set(rt_uint32_t media_mode)
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{
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rt_uint16_t phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
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if (!(media_mode & DM9000_AUTO))
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{
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switch (media_mode)
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{
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case DM9000_10MHD:
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phy_reg4 = 0x21;
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phy_reg0 = 0x0000;
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break;
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case DM9000_10MFD:
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phy_reg4 = 0x41;
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phy_reg0 = 0x1100;
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break;
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case DM9000_100MHD:
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phy_reg4 = 0x81;
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phy_reg0 = 0x2000;
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break;
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case DM9000_100MFD:
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phy_reg4 = 0x101;
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phy_reg0 = 0x3100;
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break;
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}
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phy_write(4, phy_reg4); /* Set PHY media mode */
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phy_write(0, phy_reg0); /* Tmp */
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}
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dm9000_io_write(DM9000_GPCR, 0x01); /* Let GPIO0 output */
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dm9000_io_write(DM9000_GPR, 0x00); /* Enable PHY */
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}
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/* interrupt service routine */
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void rt_dm9000_isr(int irqno)
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{
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rt_uint16_t int_status;
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rt_uint16_t last_io;
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rt_uint32_t eint_pend;
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last_io = DM9000_IO;
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/* Disable all interrupts */
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dm9000_io_write(DM9000_IMR, IMR_PAR);
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/* Got DM9000 interrupt status */
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int_status = dm9000_io_read(DM9000_ISR); /* Got ISR */
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dm9000_io_write(DM9000_ISR, int_status); /* Clear ISR status */
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DM9000_TRACE("dm9000 isr: int status %04x\n", int_status);
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/* receive overflow */
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if (int_status & ISR_ROS)
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{
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rt_kprintf("overflow\n");
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}
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if (int_status & ISR_ROOS)
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{
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rt_kprintf("overflow counter overflow\n");
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}
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/* Received the coming packet */
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if (int_status & ISR_PRS)
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{
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/* a frame has been received */
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eth_device_ready(&(dm9000_device.parent));
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}
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/* Transmit Interrupt check */
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if (int_status & ISR_PTS)
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{
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/* transmit done */
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int tx_status = dm9000_io_read(DM9000_NSR); /* Got TX status */
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if (tx_status & (NSR_TX2END | NSR_TX1END))
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{
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dm9000_device.packet_cnt --;
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if (dm9000_device.packet_cnt > 0)
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{
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DM9000_TRACE("dm9000 isr: tx second packet\n");
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/* transmit packet II */
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/* Set TX length to DM9000 */
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dm9000_io_write(DM9000_TXPLL, dm9000_device.queue_packet_len & 0xff);
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dm9000_io_write(DM9000_TXPLH, (dm9000_device.queue_packet_len >> 8) & 0xff);
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/* Issue TX polling command */
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dm9000_io_write(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
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}
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/* One packet sent complete */
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rt_sem_release(&sem_ack);
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}
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}
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/* Re-enable interrupt mask */
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dm9000_io_write(DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
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DM9000_IO = last_io;
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}
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/* RT-Thread Device Interface */
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/* initialize the interface */
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static rt_err_t rt_dm9000_init(rt_device_t dev)
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{
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int i, oft, lnk;
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rt_uint32_t value;
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/* RESET device */
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dm9000_io_write(DM9000_NCR, NCR_RST);
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delay_ms(1000); /* delay 1ms */
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/* identfy DM9000 */
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value = dm9000_io_read(DM9000_VIDL);
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value |= dm9000_io_read(DM9000_VIDH) << 8;
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value |= dm9000_io_read(DM9000_PIDL) << 16;
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value |= dm9000_io_read(DM9000_PIDH) << 24;
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if (value == DM9000_ID)
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{
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rt_kprintf("dm9000 id: 0x%x\n", value);
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}
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else
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{
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rt_kprintf("dm9000 id: 0x%x\n", value);
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return -RT_ERROR;
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}
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/* GPIO0 on pre-activate PHY */
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dm9000_io_write(DM9000_GPR, 0x00); /* REG_1F bit0 activate phyxcer */
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dm9000_io_write(DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
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dm9000_io_write(DM9000_GPR, 0x00); /* Enable PHY */
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/* Set PHY */
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phy_mode_set(dm9000_device.mode);
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/* Program operating register */
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dm9000_io_write(DM9000_NCR, 0x0); /* only intern phy supported by now */
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dm9000_io_write(DM9000_TCR, 0); /* TX Polling clear */
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dm9000_io_write(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
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dm9000_io_write(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
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dm9000_io_write(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
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dm9000_io_write(DM9000_SMCR, 0); /* Special Mode */
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dm9000_io_write(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
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dm9000_io_write(DM9000_ISR, 0x0f); /* Clear interrupt status */
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dm9000_io_write(DM9000_TCR2, 0x80); /* Switch LED to mode 1 */
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/* set mac address */
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for (i = 0, oft = 0x10; i < 6; i++, oft++)
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dm9000_io_write(oft, dm9000_device.dev_addr[i]);
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/* set multicast address */
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for (i = 0, oft = 0x16; i < 8; i++, oft++)
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dm9000_io_write(oft, 0xff);
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/* Activate DM9000 */
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dm9000_io_write(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
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dm9000_io_write(DM9000_IMR, IMR_PAR);
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if (dm9000_device.mode == DM9000_AUTO)
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{
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i = 0;
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while (!(phy_read(1) & 0x20))
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{
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/* autonegation complete bit */
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rt_thread_delay( RT_TICK_PER_SECOND/10 );
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i++;
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if (i > 30 ) /* wait 3s */
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{
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rt_kprintf("could not establish link\n");
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return 0;
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}
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}
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}
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/* send a notify */
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eth_device_linkchange(&dm9000_device.parent, RT_TRUE);
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/* see what we've got */
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lnk = phy_read(17) >> 12;
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rt_kprintf("operating at ");
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switch (lnk)
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{
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case 1:
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rt_kprintf("10M half duplex ");
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break;
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case 2:
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rt_kprintf("10M full duplex ");
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break;
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case 4:
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rt_kprintf("100M half duplex ");
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break;
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case 8:
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rt_kprintf("100M full duplex ");
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break;
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default:
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rt_kprintf("unknown: %d ", lnk);
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break;
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}
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rt_kprintf("mode\n");
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/* Enable TX/RX interrupt mask */
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dm9000_io_write(DM9000_IMR,IMR_PAR | IMR_PTM | IMR_PRM);
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return RT_EOK;
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}
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static rt_err_t rt_dm9000_open(rt_device_t dev, rt_uint16_t oflag)
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{
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return RT_EOK;
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}
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static rt_err_t rt_dm9000_close(rt_device_t dev)
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{
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/* RESET devie */
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phy_write(0, 0x8000); /* PHY RESET */
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dm9000_io_write(DM9000_GPR, 0x01); /* Power-Down PHY */
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dm9000_io_write(DM9000_IMR, 0x80); /* Disable all interrupt */
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dm9000_io_write(DM9000_RCR, 0x00); /* Disable RX */
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return RT_EOK;
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}
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static rt_ssize_t rt_dm9000_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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{
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_ssize_t rt_dm9000_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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{
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_err_t rt_dm9000_control(rt_device_t dev, int cmd, void *args)
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{
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switch (cmd)
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{
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case NIOCTL_GADDR:
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/* get mac address */
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if (args) rt_memcpy(args, dm9000_device.dev_addr, 6);
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else return -RT_ERROR;
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break;
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default :
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break;
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}
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return RT_EOK;
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}
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/* ethernet device interface */
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/* transmit packet. */
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rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
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{
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DM9000_TRACE("dm9000 tx: %d\n", p->tot_len);
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/* lock DM9000 device */
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rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
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/* disable dm9000a interrupt */
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dm9000_io_write(DM9000_IMR, IMR_PAR);
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/* Move data to DM9000 TX RAM */
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DM9000_outb(DM9000_IO_BASE, DM9000_MWCMD);
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{
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/* q traverses through linked list of pbuf's
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* This list MUST consist of a single packet ONLY */
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struct pbuf *q;
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rt_uint16_t pbuf_index = 0;
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rt_uint8_t word[2], word_index = 0;
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q = p;
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/* Write data into dm9000a, two bytes at a time
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* Handling pbuf's with odd number of bytes correctly
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* No attempt to optimize for speed has been made */
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while (q)
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{
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if (pbuf_index < q->len)
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{
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word[word_index++] = ((u8_t*)q->payload)[pbuf_index++];
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if (word_index == 2)
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{
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DM9000_outw(DM9000_DATA_BASE, (word[1] << 8) | word[0]);
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word_index = 0;
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}
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}
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else
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{
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q = q->next;
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pbuf_index = 0;
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}
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}
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/* One byte could still be unsent */
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if (word_index == 1)
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{
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DM9000_outw(DM9000_DATA_BASE, word[0]);
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}
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}
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if (dm9000_device.packet_cnt == 0)
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{
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DM9000_TRACE("dm9000 tx: first packet\n");
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dm9000_device.packet_cnt ++;
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/* Set TX length to DM9000 */
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dm9000_io_write(DM9000_TXPLL, p->tot_len & 0xff);
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dm9000_io_write(DM9000_TXPLH, (p->tot_len >> 8) & 0xff);
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/* Issue TX polling command */
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dm9000_io_write(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
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}
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else
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{
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DM9000_TRACE("dm9000 tx: second packet\n");
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dm9000_device.packet_cnt ++;
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dm9000_device.queue_packet_len = p->tot_len;
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}
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/* enable dm9000a interrupt */
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dm9000_io_write(DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
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/* unlock DM9000 device */
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rt_sem_release(&sem_lock);
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/* wait ack */
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rt_sem_take(&sem_ack, RT_WAITING_FOREVER);
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DM9000_TRACE("dm9000 tx done\n");
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return RT_EOK;
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}
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/* reception packet. */
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struct pbuf *rt_dm9000_rx(rt_device_t dev)
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{
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struct pbuf* p;
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rt_uint32_t rxbyte;
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rt_uint16_t rx_status, rx_len;
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rt_uint16_t* data;
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/* init p pointer */
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p = RT_NULL;
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/* lock DM9000 device */
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rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
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__error_retry:
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/* Check packet ready or not */
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dm9000_io_read(DM9000_MRCMDX); /* Dummy read */
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rxbyte = DM9000_inb(DM9000_DATA_BASE); /* Got most updated data */
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if (rxbyte)
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{
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if (rxbyte > 1)
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{
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DM9000_TRACE("dm9000 rx: rx error, stop device\n");
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dm9000_io_write(DM9000_RCR, 0x00); /* Stop Device */
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dm9000_io_write(DM9000_ISR, 0x80); /* Stop INT request */
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}
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/* A packet ready now & Get status/length */
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DM9000_outb(DM9000_IO_BASE, DM9000_MRCMD);
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rx_status = DM9000_inw(DM9000_DATA_BASE);
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rx_len = DM9000_inw(DM9000_DATA_BASE);
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DM9000_TRACE("dm9000 rx: status %04x len %d\n", rx_status, rx_len);
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/* allocate buffer */
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p = pbuf_alloc(PBUF_LINK, rx_len, PBUF_RAM);
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if (p != RT_NULL)
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{
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struct pbuf* q;
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rt_int32_t len;
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for (q = p; q != RT_NULL; q= q->next)
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{
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data = (rt_uint16_t*)q->payload;
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len = q->len;
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while (len > 0)
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{
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*data = DM9000_inw(DM9000_DATA_BASE);
|
|
data ++;
|
|
len -= 2;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
rt_uint16_t dummy;
|
|
|
|
rt_kprintf("dm9000 rx: no pbuf\n");
|
|
|
|
/* no pbuf, discard data from DM9000 */
|
|
data = &dummy;
|
|
while (rx_len)
|
|
{
|
|
*data = DM9000_inw(DM9000_DATA_BASE);
|
|
rx_len -= 2;
|
|
}
|
|
}
|
|
|
|
if ((rx_status & 0xbf00) || (rx_len < 0x40)
|
|
|| (rx_len > DM9000_PKT_MAX))
|
|
{
|
|
rt_kprintf("rx error: status %04x, rx_len: %d\n", rx_status, rx_len);
|
|
|
|
if (rx_status & 0x100)
|
|
{
|
|
rt_kprintf("rx fifo error\n");
|
|
}
|
|
if (rx_status & 0x200)
|
|
{
|
|
rt_kprintf("rx crc error\n");
|
|
}
|
|
if (rx_status & 0x8000)
|
|
{
|
|
rt_kprintf("rx length error\n");
|
|
}
|
|
if (rx_len > DM9000_PKT_MAX)
|
|
{
|
|
rt_kprintf("rx length too big\n");
|
|
|
|
/* RESET device */
|
|
dm9000_io_write(DM9000_NCR, NCR_RST);
|
|
rt_thread_delay(1); /* delay 5ms */
|
|
}
|
|
|
|
/* it issues an error, release pbuf */
|
|
if (p != RT_NULL) pbuf_free(p);
|
|
p = RT_NULL;
|
|
|
|
goto __error_retry;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* clear packet received latch status */
|
|
dm9000_io_write(DM9000_ISR, ISR_PTS);
|
|
|
|
/* restore receive interrupt */
|
|
dm9000_io_write(DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
|
|
}
|
|
|
|
/* unlock DM9000 device */
|
|
rt_sem_release(&sem_lock);
|
|
|
|
return p;
|
|
}
|
|
|
|
#define B4_Tacs 0x0
|
|
#define B4_Tcos 0x0
|
|
#define B4_Tacc 0x7
|
|
#define B4_Tcoh 0x0
|
|
#define B4_Tah 0x0
|
|
#define B4_Tacp 0x0
|
|
#define B4_PMC 0x0
|
|
|
|
void INTEINT4_7_handler(int irqno, void *param)
|
|
{
|
|
rt_uint32_t eint_pend;
|
|
|
|
eint_pend = EINTPEND;
|
|
|
|
/* EINT7 : DM9000AEP */
|
|
if( eint_pend & (1<<7) )
|
|
{
|
|
rt_dm9000_isr(0);
|
|
}
|
|
|
|
/* clear EINT pending bit */
|
|
EINTPEND = eint_pend;
|
|
}
|
|
|
|
int rt_hw_dm9000_init()
|
|
{
|
|
/* Set GPF7 as EINT7 */
|
|
GPFCON = GPFCON & (~(3 << 14)) | (2 << 14);
|
|
GPFUP = GPFUP | (1 << 7);
|
|
/* EINT7 High level interrupt */
|
|
EXTINT0 = (EXTINT0 & (~(0x7 << 28))) | (0x1 << 28);
|
|
/* Enable EINT7 */
|
|
EINTMASK = EINTMASK & (~(1<<7));
|
|
/* Set GPA15 as nGCS4 */
|
|
GPACON |= 1 << 15;
|
|
/* DM9000 width 16, wait enable */
|
|
BWSCON = BWSCON & (~(0x7<<16)) | (0x5<<16);
|
|
BANKCON4 = (1<<13) | (1<<11) | (0x6<<8) | (1<<6) | (1<<4) | (0<<2) | (0);
|
|
|
|
rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
|
|
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
|
|
|
|
dm9000_device.type = TYPE_DM9000A;
|
|
dm9000_device.mode = DM9000_AUTO;
|
|
dm9000_device.packet_cnt = 0;
|
|
dm9000_device.queue_packet_len = 0;
|
|
|
|
/*
|
|
* SRAM Tx/Rx pointer automatically return to start address,
|
|
* Packet Transmitted, Packet Received
|
|
*/
|
|
|
|
dm9000_device.dev_addr[0] = 0x00;
|
|
dm9000_device.dev_addr[1] = 0x60;
|
|
dm9000_device.dev_addr[2] = 0x6E;
|
|
dm9000_device.dev_addr[3] = 0x11;
|
|
dm9000_device.dev_addr[4] = 0x02;
|
|
dm9000_device.dev_addr[5] = 0x0F;
|
|
|
|
dm9000_device.parent.parent.init = rt_dm9000_init;
|
|
dm9000_device.parent.parent.open = rt_dm9000_open;
|
|
dm9000_device.parent.parent.close = rt_dm9000_close;
|
|
dm9000_device.parent.parent.read = rt_dm9000_read;
|
|
dm9000_device.parent.parent.write = rt_dm9000_write;
|
|
dm9000_device.parent.parent.control = rt_dm9000_control;
|
|
dm9000_device.parent.parent.user_data = RT_NULL;
|
|
|
|
dm9000_device.parent.eth_rx = rt_dm9000_rx;
|
|
dm9000_device.parent.eth_tx = rt_dm9000_tx;
|
|
|
|
eth_device_init(&(dm9000_device.parent), "e0");
|
|
|
|
/* instal interrupt */
|
|
rt_hw_interrupt_install(INTEINT4_7, INTEINT4_7_handler, RT_NULL, "EINT4_7");
|
|
rt_hw_interrupt_umask(INTEINT4_7);
|
|
|
|
return RT_EOK;
|
|
}
|
|
|
|
INIT_DEVICE_EXPORT(rt_hw_dm9000_init);
|
|
|
|
void dm9000a(void)
|
|
{
|
|
rt_kprintf("\n");
|
|
rt_kprintf("NCR (%02X): %02x\n", DM9000_NCR, dm9000_io_read(DM9000_NCR));
|
|
rt_kprintf("NSR (%02X): %02x\n", DM9000_NSR, dm9000_io_read(DM9000_NSR));
|
|
rt_kprintf("TCR (%02X): %02x\n", DM9000_TCR, dm9000_io_read(DM9000_TCR));
|
|
rt_kprintf("TSRI (%02X): %02x\n", DM9000_TSR1, dm9000_io_read(DM9000_TSR1));
|
|
rt_kprintf("TSRII (%02X): %02x\n", DM9000_TSR2, dm9000_io_read(DM9000_TSR2));
|
|
rt_kprintf("RCR (%02X): %02x\n", DM9000_RCR, dm9000_io_read(DM9000_RCR));
|
|
rt_kprintf("RSR (%02X): %02x\n", DM9000_RSR, dm9000_io_read(DM9000_RSR));
|
|
rt_kprintf("ORCR (%02X): %02x\n", DM9000_ROCR, dm9000_io_read(DM9000_ROCR));
|
|
rt_kprintf("CRR (%02X): %02x\n", DM9000_CHIPR, dm9000_io_read(DM9000_CHIPR));
|
|
rt_kprintf("CSCR (%02X): %02x\n", DM9000_CSCR, dm9000_io_read(DM9000_CSCR));
|
|
rt_kprintf("RCSSR (%02X): %02x\n", DM9000_RCSSR, dm9000_io_read(DM9000_RCSSR));
|
|
rt_kprintf("ISR (%02X): %02x\n", DM9000_ISR, dm9000_io_read(DM9000_ISR));
|
|
rt_kprintf("IMR (%02X): %02x\n", DM9000_IMR, dm9000_io_read(DM9000_IMR));
|
|
rt_kprintf("\n");
|
|
}
|
|
|
|
#ifdef RT_USING_FINSH
|
|
#include <finsh.h>
|
|
FINSH_FUNCTION_EXPORT(dm9000a, dm9000a register dump);
|
|
#endif
|