1004 lines
28 KiB
C
1004 lines
28 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-05-16 shelton first version
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* 2022-11-10 shelton support uart dma
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* 2023-01-31 shelton add support f421/f425
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* 2023-04-08 shelton add support f423
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* 2023-10-18 shelton add support f402/f405
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* 2024-04-12 shelton add support a403a and a423
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*/
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#include "drv_common.h"
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#include "drv_usart.h"
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#include "drv_config.h"
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#ifdef RT_USING_SERIAL
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#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \
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!defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && \
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!defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
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!defined(BSP_USING_UART7) && !defined(BSP_USING_UART8)
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#error "Please define at least one BSP_USING_UARTx"
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#endif
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enum {
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#ifdef BSP_USING_UART1
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UART1_INDEX,
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#endif
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#ifdef BSP_USING_UART2
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UART2_INDEX,
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#endif
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#ifdef BSP_USING_UART3
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UART3_INDEX,
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#endif
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#ifdef BSP_USING_UART4
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UART4_INDEX,
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#endif
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#ifdef BSP_USING_UART5
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UART5_INDEX,
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#endif
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#ifdef BSP_USING_UART6
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UART6_INDEX,
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#endif
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#ifdef BSP_USING_UART7
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UART7_INDEX,
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#endif
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#ifdef BSP_USING_UART8
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UART8_INDEX,
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#endif
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};
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static struct at32_uart uart_config[] = {
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#ifdef BSP_USING_UART1
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UART1_CONFIG,
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#endif
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#ifdef BSP_USING_UART2
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UART2_CONFIG,
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#endif
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#ifdef BSP_USING_UART3
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UART3_CONFIG,
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#endif
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#ifdef BSP_USING_UART4
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UART4_CONFIG,
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#endif
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#ifdef BSP_USING_UART5
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UART5_CONFIG,
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#endif
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#ifdef BSP_USING_UART6
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UART6_CONFIG,
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#endif
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#ifdef BSP_USING_UART7
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UART7_CONFIG,
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#endif
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#ifdef BSP_USING_UART8
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UART8_CONFIG,
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#endif
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};
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#ifdef RT_SERIAL_USING_DMA
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static void at32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
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#endif
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static rt_err_t at32_configure(struct rt_serial_device *serial,
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struct serial_configure *cfg) {
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usart_data_bit_num_type data_bit;
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usart_stop_bit_num_type stop_bit;
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usart_parity_selection_type parity_mode;
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usart_hardware_flow_control_type flow_control;
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RT_ASSERT(serial != RT_NULL);
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RT_ASSERT(cfg != RT_NULL);
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struct at32_uart *instance = rt_container_of(serial, struct at32_uart, serial);
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RT_ASSERT(instance != RT_NULL);
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at32_msp_usart_init((void *)instance->uart_x);
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usart_receiver_enable(instance->uart_x, TRUE);
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usart_transmitter_enable(instance->uart_x, TRUE);
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switch (cfg->data_bits) {
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case DATA_BITS_8:
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data_bit = USART_DATA_8BITS;
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break;
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case DATA_BITS_9:
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data_bit = USART_DATA_9BITS;
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break;
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default:
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data_bit = USART_DATA_8BITS;
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break;
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}
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switch (cfg->stop_bits) {
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case STOP_BITS_1:
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stop_bit = USART_STOP_1_BIT;
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break;
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case STOP_BITS_2:
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stop_bit = USART_STOP_2_BIT;
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break;
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default:
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stop_bit = USART_STOP_1_BIT;
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break;
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}
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switch (cfg->parity) {
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case PARITY_NONE:
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parity_mode = USART_PARITY_NONE;
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break;
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case PARITY_ODD:
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parity_mode = USART_PARITY_ODD;
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break;
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case PARITY_EVEN:
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parity_mode = USART_PARITY_EVEN;
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break;
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default:
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parity_mode = USART_PARITY_NONE;
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break;
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}
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switch (cfg->flowcontrol) {
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case RT_SERIAL_FLOWCONTROL_NONE:
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flow_control = USART_HARDWARE_FLOW_NONE;
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break;
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case RT_SERIAL_FLOWCONTROL_CTSRTS:
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flow_control = USART_HARDWARE_FLOW_RTS_CTS;
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break;
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default:
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flow_control = USART_HARDWARE_FLOW_NONE;
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break;
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}
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#ifdef RT_SERIAL_USING_DMA
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if (!(serial->parent.open_flag & RT_DEVICE_OFLAG_OPEN)) {
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instance->last_index = 0;
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}
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#endif
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usart_hardware_flow_control_set(instance->uart_x, flow_control);
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usart_parity_selection_config(instance->uart_x, parity_mode);
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usart_init(instance->uart_x, cfg->baud_rate, data_bit, stop_bit);
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usart_enable(instance->uart_x, TRUE);
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return RT_EOK;
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}
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static rt_err_t at32_control(struct rt_serial_device *serial, int cmd, void *arg) {
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struct at32_uart *instance;
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#ifdef RT_SERIAL_USING_DMA
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rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
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#endif
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RT_ASSERT(serial != RT_NULL);
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instance = rt_container_of(serial, struct at32_uart, serial);
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RT_ASSERT(instance != RT_NULL);
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switch (cmd) {
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case RT_DEVICE_CTRL_CLR_INT:
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nvic_irq_disable(instance->irqn);
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usart_interrupt_enable(instance->uart_x, USART_RDBF_INT, FALSE);
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#ifdef RT_SERIAL_USING_DMA
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/* disable DMA */
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if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
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{
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nvic_irq_disable(instance->dma_rx->dma_irqn);
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dma_reset(instance->dma_rx->dma_channel);
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}
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else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
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{
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nvic_irq_disable(instance->dma_tx->dma_irqn);
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dma_reset(instance->dma_tx->dma_channel);
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}
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#endif
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break;
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case RT_DEVICE_CTRL_SET_INT:
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nvic_irq_enable(instance->irqn, 1, 0);
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usart_interrupt_enable(instance->uart_x, USART_RDBF_INT, TRUE);
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break;
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#ifdef RT_SERIAL_USING_DMA
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case RT_DEVICE_CTRL_CONFIG:
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at32_dma_config(serial, ctrl_arg);
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break;
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#endif
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}
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return RT_EOK;
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}
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static int at32_putc(struct rt_serial_device *serial, char ch) {
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struct at32_uart *instance;
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RT_ASSERT(serial != RT_NULL);
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instance = rt_container_of(serial, struct at32_uart, serial);
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RT_ASSERT(instance != RT_NULL);
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usart_data_transmit(instance->uart_x, (uint8_t)ch);
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while (usart_flag_get(instance->uart_x, USART_TDC_FLAG) == RESET);
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return 1;
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}
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static int at32_getc(struct rt_serial_device *serial) {
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int ch;
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struct at32_uart *instance;
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RT_ASSERT(serial != RT_NULL);
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instance = rt_container_of(serial, struct at32_uart, serial);
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RT_ASSERT(instance != RT_NULL);
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ch = -1;
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if (usart_flag_get(instance->uart_x, USART_RDBF_FLAG) != RESET) {
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ch = usart_data_receive(instance->uart_x) & 0xff;
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}
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return ch;
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}
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#ifdef RT_SERIAL_USING_DMA
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static void _uart_dma_receive(struct at32_uart *instance, rt_uint8_t *buffer, rt_uint32_t size)
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{
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dma_channel_type* dma_channel = instance->dma_rx->dma_channel;
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dma_channel->dtcnt = size;
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dma_channel->paddr = (rt_uint32_t)&(instance->uart_x->dt);
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dma_channel->maddr = (rt_uint32_t)buffer;
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/* enable usart interrupt */
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usart_interrupt_enable(instance->uart_x, USART_PERR_INT, TRUE);
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usart_interrupt_enable(instance->uart_x, USART_IDLE_INT, TRUE);
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/* enable transmit complete interrupt */
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dma_interrupt_enable(dma_channel, DMA_FDT_INT, TRUE);
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/* enable dma receive */
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usart_dma_receiver_enable(instance->uart_x, TRUE);
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/* enable dma channel */
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dma_channel_enable(dma_channel, TRUE);
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}
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static void _uart_dma_transmit(struct at32_uart *instance, rt_uint8_t *buffer, rt_uint32_t size)
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{
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/* wait before transfer complete */
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while(instance->dma_tx->dma_done == RT_FALSE);
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dma_channel_type *dma_channel = instance->dma_tx->dma_channel;
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dma_channel->dtcnt = size;
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dma_channel->paddr = (rt_uint32_t)&(instance->uart_x->dt);
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dma_channel->maddr = (rt_uint32_t)buffer;
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/* enable transmit complete interrupt */
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dma_interrupt_enable(dma_channel, DMA_FDT_INT, TRUE);
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/* enable dma transmit */
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usart_dma_transmitter_enable(instance->uart_x, TRUE);
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/* mark dma flag */
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instance->dma_tx->dma_done = RT_FALSE;
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/* enable dma channel */
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dma_channel_enable(dma_channel, TRUE);
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}
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static void at32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
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{
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dma_init_type dma_init_struct;
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dma_channel_type *dma_channel = NULL;
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struct rt_serial_rx_fifo *rx_fifo;
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struct at32_uart *instance;
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struct dma_config *dma_config;
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RT_ASSERT(serial != RT_NULL);
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instance = rt_container_of(serial, struct at32_uart, serial);
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RT_ASSERT(instance != RT_NULL);
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RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
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if (RT_DEVICE_FLAG_DMA_RX == flag)
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{
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dma_channel = instance->dma_rx->dma_channel;
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dma_config = instance->dma_rx;
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}
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else /* RT_DEVICE_FLAG_DMA_TX == flag */
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{
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dma_channel = instance->dma_tx->dma_channel;
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dma_config = instance->dma_tx;
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}
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crm_periph_clock_enable(dma_config->dma_clock, TRUE);
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dma_default_para_init(&dma_init_struct);
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dma_init_struct.peripheral_inc_enable = FALSE;
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dma_init_struct.memory_inc_enable = TRUE;
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dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
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dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
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dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
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if (RT_DEVICE_FLAG_DMA_RX == flag)
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{
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dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
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dma_init_struct.loop_mode_enable = TRUE;
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}
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else if (RT_DEVICE_FLAG_DMA_TX == flag)
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{
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dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
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dma_init_struct.loop_mode_enable = FALSE;
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}
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dma_reset(dma_channel);
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dma_init(dma_channel, &dma_init_struct);
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#if defined (SOC_SERIES_AT32F425)
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dma_flexible_config(dma_config->dma_x, dma_config->flex_channel, \
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(dma_flexible_request_type)dma_config->request_id);
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#endif
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#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
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defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
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defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423)
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dmamux_enable(dma_config->dma_x, TRUE);
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dmamux_init(dma_config->dmamux_channel, (dmamux_requst_id_sel_type)dma_config->request_id);
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#endif
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/* enable interrupt */
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if (flag == RT_DEVICE_FLAG_DMA_RX)
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{
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rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
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/* start dma transfer */
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_uart_dma_receive(instance, rx_fifo->buffer, serial->config.bufsz);
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}
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/* dma irq should set in dma tx mode */
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nvic_irq_enable(dma_config->dma_irqn, 0, 0);
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nvic_irq_enable(instance->irqn, 1, 0);
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}
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static rt_ssize_t at32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
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{
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struct at32_uart *instance;
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RT_ASSERT(serial != RT_NULL);
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instance = rt_container_of(serial, struct at32_uart, serial);
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RT_ASSERT(instance != RT_NULL);
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RT_ASSERT(buf != RT_NULL);
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if (size == 0)
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{
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return 0;
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}
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if (RT_SERIAL_DMA_TX == direction)
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{
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_uart_dma_transmit(instance, buf, size);
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}
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return size;
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}
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#endif
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static const struct rt_uart_ops at32_uart_ops = {
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at32_configure,
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at32_control,
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at32_putc,
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at32_getc,
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#ifdef RT_SERIAL_USING_DMA
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at32_dma_transmit,
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#endif
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};
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#ifdef RT_SERIAL_USING_DMA
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void dma_rx_isr(struct rt_serial_device *serial)
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{
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volatile rt_uint32_t reg_sts = 0, index = 0;
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rt_size_t recv_total_index, recv_len;
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rt_base_t level;
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struct at32_uart *instance;
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RT_ASSERT(serial != RT_NULL);
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instance = rt_container_of(serial, struct at32_uart, serial);
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RT_ASSERT(instance != RT_NULL);
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reg_sts = instance->dma_rx->dma_x->sts;
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index = instance->dma_rx->channel_index;
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if (((reg_sts & (DMA_FDT_FLAG << (4 * (index - 1)))) != RESET) ||
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((reg_sts & (DMA_HDT_FLAG << (4 * (index - 1)))) != RESET))
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{
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/* clear dma flag */
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instance->dma_rx->dma_x->clr |= (rt_uint32_t)(DMA_FDT_FLAG << (4 * (index - 1))) | (DMA_HDT_FLAG << (4 * (index - 1)));
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level = rt_hw_interrupt_disable();
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recv_total_index = serial->config.bufsz - dma_data_number_get(instance->dma_rx->dma_channel);
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if (recv_total_index == 0)
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{
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recv_len = serial->config.bufsz - instance->last_index;
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}
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else
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{
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recv_len = recv_total_index - instance->last_index;
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}
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instance->last_index = recv_total_index;
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rt_hw_interrupt_enable(level);
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if (recv_len)
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{
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
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}
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}
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}
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void dma_tx_isr(struct rt_serial_device *serial)
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{
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volatile rt_uint32_t reg_sts = 0, index = 0;
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rt_size_t trans_total_index;
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rt_base_t level;
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struct at32_uart *instance;
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RT_ASSERT(serial != RT_NULL);
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instance = rt_container_of(serial, struct at32_uart, serial);
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RT_ASSERT(instance != RT_NULL);
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reg_sts = instance->dma_tx->dma_x->sts;
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index = instance->dma_tx->channel_index;
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if ((reg_sts & (DMA_FDT_FLAG << (4 * (index - 1)))) != RESET)
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{
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/* mark dma flag */
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instance->dma_tx->dma_done = RT_TRUE;
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/* clear dma flag */
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instance->dma_tx->dma_x->clr |= (rt_uint32_t)(DMA_FDT_FLAG << (4 * (index - 1)));
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/* disable dma tx channel */
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dma_channel_enable(instance->dma_tx->dma_channel, FALSE);
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level = rt_hw_interrupt_disable();
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trans_total_index = dma_data_number_get(instance->dma_tx->dma_channel);
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rt_hw_interrupt_enable(level);
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if (trans_total_index == 0)
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{
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
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}
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}
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}
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#endif
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static void usart_isr(struct rt_serial_device *serial) {
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struct at32_uart *instance;
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#ifdef RT_SERIAL_USING_DMA
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rt_size_t recv_total_index, recv_len;
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rt_base_t level;
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#endif
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RT_ASSERT(serial != RT_NULL);
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instance = rt_container_of(serial, struct at32_uart, serial);
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RT_ASSERT(instance != RT_NULL);
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if (usart_flag_get(instance->uart_x, USART_RDBF_FLAG) != RESET) {
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
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}
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#ifdef RT_SERIAL_USING_DMA
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else if (usart_flag_get(instance->uart_x, USART_IDLEF_FLAG) != RESET)
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{
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/* clear idle flag */
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usart_data_receive(instance->uart_x);
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level = rt_hw_interrupt_disable();
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recv_total_index = serial->config.bufsz - dma_data_number_get(instance->dma_rx->dma_channel);
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recv_len = recv_total_index - instance->last_index;
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instance->last_index = recv_total_index;
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rt_hw_interrupt_enable(level);
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|
|
|
if (recv_len)
|
|
{
|
|
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
|
|
}
|
|
}
|
|
#endif
|
|
else
|
|
{
|
|
if (usart_flag_get(instance->uart_x, USART_CTSCF_FLAG) != RESET) {
|
|
usart_flag_clear(instance->uart_x, USART_CTSCF_FLAG);
|
|
}
|
|
|
|
if (usart_flag_get(instance->uart_x, USART_BFF_FLAG) != RESET) {
|
|
usart_flag_clear(instance->uart_x, USART_BFF_FLAG);
|
|
}
|
|
}
|
|
}
|
|
|
|
#ifdef BSP_USING_UART1
|
|
void UART1_IRQHandler(void) {
|
|
rt_interrupt_enter();
|
|
|
|
usart_isr(&uart_config[UART1_INDEX].serial);
|
|
|
|
rt_interrupt_leave();
|
|
}
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
|
|
void UART1_RX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_rx_isr(&uart_config[UART1_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
|
|
void UART1_TX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_tx_isr(&uart_config[UART1_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
|
|
#endif
|
|
#ifdef BSP_USING_UART2
|
|
void UART2_IRQHandler(void) {
|
|
rt_interrupt_enter();
|
|
|
|
usart_isr(&uart_config[UART2_INDEX].serial);
|
|
|
|
rt_interrupt_leave();
|
|
}
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
|
|
void UART2_RX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_rx_isr(&uart_config[UART2_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
|
|
void UART2_TX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_tx_isr(&uart_config[UART2_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
|
|
#endif
|
|
#ifdef BSP_USING_UART3
|
|
void UART3_IRQHandler(void) {
|
|
rt_interrupt_enter();
|
|
|
|
usart_isr(&uart_config[UART3_INDEX].serial);
|
|
|
|
rt_interrupt_leave();
|
|
}
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
|
|
void UART3_RX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_rx_isr(&uart_config[UART3_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA) */
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
|
|
void UART3_TX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_tx_isr(&uart_config[UART3_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA) */
|
|
#endif
|
|
#ifdef BSP_USING_UART4
|
|
void UART4_IRQHandler(void) {
|
|
rt_interrupt_enter();
|
|
|
|
usart_isr(&uart_config[UART4_INDEX].serial);
|
|
|
|
rt_interrupt_leave();
|
|
}
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
|
|
void UART4_RX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_rx_isr(&uart_config[UART4_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA) */
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
|
|
void UART4_TX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_tx_isr(&uart_config[UART4_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART14_TX_USING_DMA) */
|
|
#endif
|
|
#ifdef BSP_USING_UART5
|
|
void UART5_IRQHandler(void) {
|
|
rt_interrupt_enter();
|
|
|
|
usart_isr(&uart_config[UART5_INDEX].serial);
|
|
|
|
rt_interrupt_leave();
|
|
}
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
|
|
void UART5_RX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_rx_isr(&uart_config[UART5_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
|
|
void UART5_TX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_tx_isr(&uart_config[UART5_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
|
|
#endif
|
|
#ifdef BSP_USING_UART6
|
|
void UART6_IRQHandler(void) {
|
|
rt_interrupt_enter();
|
|
|
|
usart_isr(&uart_config[UART6_INDEX].serial);
|
|
|
|
rt_interrupt_leave();
|
|
}
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
|
|
void UART6_RX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_rx_isr(&uart_config[UART6_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
|
|
void UART6_TX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_tx_isr(&uart_config[UART6_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
|
|
#endif
|
|
#ifdef BSP_USING_UART7
|
|
void UART7_IRQHandler(void) {
|
|
rt_interrupt_enter();
|
|
|
|
usart_isr(&uart_config[UART7_INDEX].serial);
|
|
|
|
rt_interrupt_leave();
|
|
}
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
|
|
void UART7_RX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_rx_isr(&uart_config[UART7_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
|
|
void UART7_TX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_tx_isr(&uart_config[UART7_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
|
|
#endif
|
|
#ifdef BSP_USING_UART8
|
|
void UART8_IRQHandler(void) {
|
|
rt_interrupt_enter();
|
|
|
|
usart_isr(&uart_config[UART8_INDEX].serial);
|
|
|
|
rt_interrupt_leave();
|
|
}
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
|
|
void UART8_RX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_rx_isr(&uart_config[UART8_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
|
|
void UART8_TX_DMA_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
dma_tx_isr(&uart_config[UART8_INDEX].serial);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
|
|
#endif
|
|
|
|
#if defined (SOC_SERIES_AT32F421)
|
|
void UART1_TX_RX_DMA_IRQHandler(void)
|
|
{
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
|
|
UART1_TX_DMA_IRQHandler();
|
|
#endif
|
|
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
|
|
UART1_RX_DMA_IRQHandler();
|
|
#endif
|
|
}
|
|
|
|
void UART2_TX_RX_DMA_IRQHandler(void)
|
|
{
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
|
|
UART2_TX_DMA_IRQHandler();
|
|
#endif
|
|
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
|
|
UART2_RX_DMA_IRQHandler();
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if defined (SOC_SERIES_AT32F425)
|
|
#if defined(BSP_USING_UART3) || defined(BSP_USING_UART4)
|
|
void USART4_3_IRQHandler(void)
|
|
{
|
|
#if defined(BSP_USING_UART3)
|
|
UART3_IRQHandler();
|
|
#endif
|
|
#if defined(BSP_USING_UART4)
|
|
UART4_IRQHandler();
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
void UART1_TX_RX_DMA_IRQHandler(void)
|
|
{
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
|
|
UART1_TX_DMA_IRQHandler();
|
|
#endif
|
|
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
|
|
UART1_RX_DMA_IRQHandler();
|
|
#endif
|
|
}
|
|
|
|
void UART3_2_TX_RX_DMA_IRQHandler(void)
|
|
{
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
|
|
UART2_TX_DMA_IRQHandler();
|
|
#endif
|
|
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
|
|
UART2_RX_DMA_IRQHandler();
|
|
#endif
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
|
|
UART3_TX_DMA_IRQHandler();
|
|
#endif
|
|
|
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
|
|
UART3_RX_DMA_IRQHandler();
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if defined (RT_SERIAL_USING_DMA)
|
|
static void _dma_base_channel_check(struct at32_uart *instance)
|
|
{
|
|
dma_channel_type *rx_channel = instance->dma_rx->dma_channel;
|
|
dma_channel_type *tx_channel = instance->dma_tx->dma_channel;
|
|
|
|
instance->dma_rx->dma_done = RT_TRUE;
|
|
instance->dma_rx->dma_x = (dma_type *)((rt_uint32_t)rx_channel & ~0xFF);
|
|
instance->dma_rx->channel_index = ((((rt_uint32_t)rx_channel & 0xFF) - 8) / 0x14) + 1;
|
|
|
|
instance->dma_tx->dma_done = RT_TRUE;
|
|
instance->dma_tx->dma_x = (dma_type *)((rt_uint32_t)tx_channel & ~0xFF);
|
|
instance->dma_tx->channel_index = ((((rt_uint32_t)tx_channel & 0xFF) - 8) / 0x14) + 1;
|
|
}
|
|
#endif
|
|
|
|
static void at32_uart_get_dma_config(void)
|
|
{
|
|
#ifdef BSP_USING_UART1
|
|
uart_config[UART1_INDEX].uart_dma_flag = 0;
|
|
#ifdef BSP_UART1_RX_USING_DMA
|
|
uart_config[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
static struct dma_config uart1_dma_rx = UART1_RX_DMA_CONFIG;
|
|
uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
|
|
#endif
|
|
#ifdef BSP_UART1_TX_USING_DMA
|
|
uart_config[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
static struct dma_config uart1_dma_tx = UART1_TX_DMA_CONFIG;
|
|
uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef BSP_USING_UART2
|
|
uart_config[UART2_INDEX].uart_dma_flag = 0;
|
|
#ifdef BSP_UART2_RX_USING_DMA
|
|
uart_config[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
static struct dma_config uart2_dma_rx = UART2_RX_DMA_CONFIG;
|
|
uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
|
|
#endif
|
|
#ifdef BSP_UART2_TX_USING_DMA
|
|
uart_config[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
static struct dma_config uart2_dma_tx = UART2_TX_DMA_CONFIG;
|
|
uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef BSP_USING_UART3
|
|
uart_config[UART3_INDEX].uart_dma_flag = 0;
|
|
#ifdef BSP_UART3_RX_USING_DMA
|
|
uart_config[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
static struct dma_config uart3_dma_rx = UART3_RX_DMA_CONFIG;
|
|
uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
|
|
#endif
|
|
#ifdef BSP_UART3_TX_USING_DMA
|
|
uart_config[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
static struct dma_config uart3_dma_tx = UART3_TX_DMA_CONFIG;
|
|
uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef BSP_USING_UART4
|
|
uart_config[UART4_INDEX].uart_dma_flag = 0;
|
|
#ifdef BSP_UART4_RX_USING_DMA
|
|
uart_config[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
static struct dma_config uart4_dma_rx = UART4_RX_DMA_CONFIG;
|
|
uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
|
|
#endif
|
|
#ifdef BSP_UART4_TX_USING_DMA
|
|
uart_config[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
static struct dma_config uart4_dma_tx = UART4_TX_DMA_CONFIG;
|
|
uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef BSP_USING_UART5
|
|
uart_config[UART5_INDEX].uart_dma_flag = 0;
|
|
#ifdef BSP_UART5_RX_USING_DMA
|
|
uart_config[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
static struct dma_config uart5_dma_rx = UART5_RX_DMA_CONFIG;
|
|
uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
|
|
#endif
|
|
#ifdef BSP_UART5_TX_USING_DMA
|
|
uart_config[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
static struct dma_config uart5_dma_tx = UART5_TX_DMA_CONFIG;
|
|
uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef BSP_USING_UART6
|
|
uart_config[UART6_INDEX].uart_dma_flag = 0;
|
|
#ifdef BSP_UART6_RX_USING_DMA
|
|
uart_config[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
static struct dma_config uart6_dma_rx = UART6_RX_DMA_CONFIG;
|
|
uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
|
|
#endif
|
|
#ifdef BSP_UART6_TX_USING_DMA
|
|
uart_config[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
static struct dma_config uart6_dma_tx = UART6_TX_DMA_CONFIG;
|
|
uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef BSP_USING_UART7
|
|
uart_config[UART7_INDEX].uart_dma_flag = 0;
|
|
#ifdef BSP_UART7_RX_USING_DMA
|
|
uart_config[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
static struct dma_config uart7_dma_rx = UART7_RX_DMA_CONFIG;
|
|
uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx;
|
|
#endif
|
|
#ifdef BSP_UART7_TX_USING_DMA
|
|
uart_config[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
static struct dma_config uart7_dma_tx = UART7_TX_DMA_CONFIG;
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uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx;
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#endif
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#endif
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#ifdef BSP_USING_UART8
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uart_config[UART8_INDEX].uart_dma_flag = 0;
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#ifdef BSP_UART8_RX_USING_DMA
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uart_config[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
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static struct dma_config uart8_dma_rx = UART8_RX_DMA_CONFIG;
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uart_config[UART8_INDEX].dma_rx = &uart8_dma_rx;
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#endif
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#ifdef BSP_UART8_TX_USING_DMA
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uart_config[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
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static struct dma_config uart8_dma_tx = UART8_TX_DMA_CONFIG;
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uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
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#endif
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#endif
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}
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int rt_hw_usart_init(void) {
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rt_size_t obj_num;
|
|
int index;
|
|
|
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obj_num = sizeof(uart_config) / sizeof(struct at32_uart);
|
|
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
|
rt_err_t result = 0;
|
|
|
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at32_uart_get_dma_config();
|
|
|
|
for (index = 0; index < obj_num; index++) {
|
|
uart_config[index].serial.ops = &at32_uart_ops;
|
|
uart_config[index].serial.config = config;
|
|
|
|
#if defined (RT_SERIAL_USING_DMA)
|
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/* search dma base and channel index */
|
|
_dma_base_channel_check(&uart_config[index]);
|
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#endif
|
|
/* register uart device */
|
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result = rt_hw_serial_register(&uart_config[index].serial,
|
|
uart_config[index].name,
|
|
RT_DEVICE_FLAG_RDWR |
|
|
RT_DEVICE_FLAG_INT_RX |
|
|
uart_config[index].uart_dma_flag ,
|
|
&uart_config[index]);
|
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RT_ASSERT(result == RT_EOK);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
#endif /* BSP_USING_SERIAL */
|