489 lines
13 KiB
C
489 lines
13 KiB
C
/**************************************************************************//**
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*
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* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-8-16 Wayne First version
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*
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******************************************************************************/
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#include <rtconfig.h>
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#if defined(BSP_USING_CCAP)
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#include <rthw.h>
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#include "NuMicro.h"
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#include "ccap_sensor.h"
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#include "drv_ccap.h"
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#define LOG_TAG "drv.ccap"
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#define DBG_ENABLE
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#define DBG_SECTION_NAME LOG_TAG
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#define DBG_LEVEL LOG_LVL_INFO
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#define DBG_COLOR
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#include <rtdbg.h>
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/* Private Typedef --------------------------------------------------------------*/
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enum
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{
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CCAP_START = -1,
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#if defined(BSP_USING_CCAP0)
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CCAP0_IDX,
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#endif
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CCAP_CNT
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};
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struct nu_ccap
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{
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struct rt_device device;
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char *name;
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CCAP_T *base;
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uint32_t rstidx;
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uint32_t modid_ccap;
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uint32_t modid_sensor;
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IRQn_Type irqn;
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ccap_config sConfig;
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};
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typedef struct nu_ccap *nu_ccap_t;
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static struct nu_ccap nu_ccap_arr [] =
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{
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#if defined(BSP_USING_CCAP0)
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{
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.name = "ccap0",
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.base = CCAP,
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.rstidx = CCAP_RST,
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.modid_ccap = CCAP_MODULE,
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.modid_sensor = SEN_MODULE,
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.irqn = CCAP_IRQn,
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},
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#endif
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};
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static void nu_ccap_isr(nu_ccap_t ccap)
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{
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CCAP_T *base = ccap->base;
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uint32_t u32CapInt, u32EvtMsk;
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u32CapInt = base->INT;
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u32EvtMsk = 0;
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if ((u32CapInt & (CCAP_INT_VIEN_Msk | CCAP_INT_VINTF_Msk)) == (CCAP_INT_VIEN_Msk | CCAP_INT_VINTF_Msk))
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{
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base->INT |= CCAP_INT_VINTF_Msk; /* Clear Frame end interrupt */
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u32EvtMsk |= NU_CCAP_FRAME_END;
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}
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if ((u32CapInt & (CCAP_INT_ADDRMIEN_Msk | CCAP_INT_ADDRMINTF_Msk)) == (CCAP_INT_ADDRMIEN_Msk | CCAP_INT_ADDRMINTF_Msk))
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{
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base->INT |= CCAP_INT_ADDRMINTF_Msk; /* Clear Address match interrupt */
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u32EvtMsk |= NU_CCAP_ADDRESS_MATCH;
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}
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if ((u32CapInt & (CCAP_INT_MEIEN_Msk | CCAP_INT_MEINTF_Msk)) == (CCAP_INT_MEIEN_Msk | CCAP_INT_MEINTF_Msk))
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{
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base->INT |= CCAP_INT_MEINTF_Msk; /* Clear Memory error interrupt */
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u32EvtMsk |= NU_CCAP_MEMORY_ERROR;
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}
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/* Invoke callback */
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if (ccap->device.rx_indicate != RT_NULL)
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ccap->device.rx_indicate(&ccap->device, 1);
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if (ccap->sConfig.pfnEvHndler && u32EvtMsk)
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ccap->sConfig.pfnEvHndler(ccap->sConfig.pvData, u32EvtMsk);
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base->CTL = base->CTL | CCAP_CTL_UPDATE;
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}
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#if defined(BSP_USING_CCAP0)
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/* CCAP interrupt entry */
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void CCAP_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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nu_ccap_isr(&nu_ccap_arr[CCAP0_IDX]);
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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/* common device interface */
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static rt_err_t ccap_init(rt_device_t dev)
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{
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return RT_EOK;
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}
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static void ccap_sensor_setfreq(nu_ccap_t psNuCcap, uint32_t u32SensorFreq)
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{
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uint32_t u32RegLockLevel = SYS_IsRegLocked();
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/* Unlock protected registers */
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if (u32RegLockLevel)
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SYS_UnlockReg();
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if (u32SensorFreq > 0)
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{
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int32_t i32Div;
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/* Specified sensor clock */
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i32Div = CLK_GetHCLKFreq() / u32SensorFreq;
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if (i32Div == 0)
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i32Div = 1;
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CLK_EnableModuleClock(psNuCcap->modid_ccap);
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CLK_SetModuleClock(psNuCcap->modid_ccap, CLK_CLKSEL0_CCAPSEL_HCLK, MODULE_NoMsk);
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CLK_EnableModuleClock(psNuCcap->modid_sensor);
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CLK_SetModuleClock(psNuCcap->modid_sensor, MODULE_NoMsk, CLK_CLKDIV3_VSENSE(i32Div));
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LOG_I("CCAP Engine clock:%d", CLK_GetHCLKFreq());
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LOG_I("CCAP Sensor preferred clock %d, divider:%d", u32SensorFreq, i32Div);
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LOG_I("CCAP Sensor actully clock:%d", CLK_GetHCLKFreq() / i32Div);
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}
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else
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{
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CLK_DisableModuleClock(psNuCcap->modid_ccap);
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CLK_DisableModuleClock(psNuCcap->modid_sensor);
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}
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/* Lock protected registers */
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if (u32RegLockLevel)
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SYS_LockReg();
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}
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static rt_err_t ccap_pipe_configure(nu_ccap_t psNuCcap, ccap_view_info_t psViewInfo)
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{
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sensor_mode_info_t psSensorModeInfo = (sensor_mode_info_t)psViewInfo;
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ccap_config_t psCcapConf = &psNuCcap->sConfig;
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uint32_t u32PipeEnabling = 0;
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struct rt_device_rect_info *psRectCropping = &psCcapConf->sRectCropping;
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/* Set Cropping Window Vertical/Horizontal Starting Address and Cropping Window Size */
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CCAP_SetCroppingWindow(psNuCcap->base, psRectCropping->y, psRectCropping->x, psRectCropping->height, psRectCropping->width);
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if (psCcapConf->sPipeInfo_Packet.pu8FarmAddr)
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{
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uint32_t u32WM, u32WN, u32HM, u32HN;
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/* Set System Memory Packet Base Address Register */
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CCAP_SetPacketBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Packet.pu8FarmAddr);
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u32WM = u32WN = u32HM = u32HN = 0;
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/* Set Packet Scaling Vertical/Horizontal Factor Register */
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if (psCcapConf->sPipeInfo_Packet.u32Height < psRectCropping->height)
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{
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u32HN = psCcapConf->sPipeInfo_Packet.u32Height;
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u32HM = psRectCropping->height;
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}
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if (psCcapConf->sPipeInfo_Packet.u32Width < psRectCropping->width)
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{
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u32WN = psCcapConf->sPipeInfo_Packet.u32Width;
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u32WM = psRectCropping->width;
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}
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CCAP_SetPacketScaling(psNuCcap->base,
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u32HN,
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u32HM,
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u32WN,
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u32WM);
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/* Set Packet Frame Output Pixel Stride Width */
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CCAP_SetPacketStride(psNuCcap->base, psCcapConf->u32Stride_Packet);
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u32PipeEnabling |= CCAP_CTL_PKTEN;
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}
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if (psCcapConf->sPipeInfo_Planar.pu8FarmAddr)
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{
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uint32_t u32Offset = 0;
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uint32_t u32WM, u32WN, u32HM, u32HN;
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uint32_t u32Div = 0;
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if (psCcapConf->sPipeInfo_Planar.u32PixFmt == CCAP_PAR_PLNFMT_YUV422)
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{
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/* U/V farm size equals Y/2 farm size */
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u32Div = 2;
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}
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else if (psCcapConf->sPipeInfo_Planar.u32PixFmt == CCAP_PAR_PLNFMT_YUV420)
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{
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/* U/V farm size equals Y/4 farm size */
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u32Div = 4;
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}
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else
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{
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goto fail_ccap_pipe_configure;
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}
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/* Set System Memory Planar Y Base Address Register */
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CCAP_SetPlanarYBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset);
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u32Offset = psCcapConf->sPipeInfo_Planar.u32Height * psCcapConf->sPipeInfo_Planar.u32Width;
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/* Set System Memory Planar U Base Address Register */
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CCAP_SetPlanarUBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset);
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u32Offset += ((psCcapConf->sPipeInfo_Planar.u32Height * psCcapConf->sPipeInfo_Planar.u32Width) / u32Div);
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/* Set System Memory Planar V Base Address Register */
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CCAP_SetPlanarVBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset);
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u32WM = u32WN = u32HM = u32HN = 0;
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/* Set Planar Scaling Vertical/Horizontal Factor Register */
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if (psCcapConf->sPipeInfo_Planar.u32Height < psRectCropping->height)
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{
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u32HN = psCcapConf->sPipeInfo_Planar.u32Height;
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u32HM = psRectCropping->height;
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}
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if (psCcapConf->sPipeInfo_Planar.u32Width < psRectCropping->width)
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{
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u32WN = psCcapConf->sPipeInfo_Planar.u32Width;
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u32WM = psRectCropping->width;
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}
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/* Set Planar Scaling Vertical/Horizontal Factor Register */
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CCAP_SetPlanarScaling(psNuCcap->base,
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u32HN,
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u32HM,
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u32WN,
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u32WM);
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/* Set Planar Frame Output Pixel Stride Width */
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CCAP_SetPlanarStride(psNuCcap->base, psCcapConf->u32Stride_Planar);
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u32PipeEnabling |= CCAP_CTL_PLNEN;
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}
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/* Set Vsync polarity, Hsync polarity, pixel clock polarity, Sensor Format and Order */
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CCAP_Open(psNuCcap->base,
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psSensorModeInfo->u32Polarity |
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psViewInfo->u32PixFmt |
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psCcapConf->sPipeInfo_Packet.u32PixFmt |
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psCcapConf->sPipeInfo_Planar.u32PixFmt,
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u32PipeEnabling);
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return RT_EOK;
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fail_ccap_pipe_configure:
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return -RT_ERROR;
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}
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static rt_err_t ccap_open(rt_device_t dev, rt_uint16_t oflag)
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{
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nu_ccap_t psNuCcap = (nu_ccap_t)dev;
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uint32_t u32RegLockLevel = SYS_IsRegLocked();
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/* Unlock protected registers */
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if (u32RegLockLevel)
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SYS_UnlockReg();
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/* Enable clock */
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ccap_sensor_setfreq(psNuCcap, 24000000);
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/* Reset IP */
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SYS_ResetModule(psNuCcap->rstidx);
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/* Lock protected registers */
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if (u32RegLockLevel)
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SYS_LockReg();
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/* Unmask External CCAP Interrupt */
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NVIC_EnableIRQ(psNuCcap->irqn);
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return RT_EOK;
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}
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static rt_err_t ccap_close(rt_device_t dev)
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{
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nu_ccap_t psNuCcap = (nu_ccap_t)dev;
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/* Stop capture engine */
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CCAP_Stop(psNuCcap->base, FALSE);
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/* Disable CCAP Interrupt */
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CCAP_DisableInt(psNuCcap->base, CCAP_INT_VIEN_Msk);
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/* Mask External CCAP Interrupt */
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NVIC_DisableIRQ(psNuCcap->irqn);
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/* Disable clock */
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ccap_sensor_setfreq(psNuCcap, 0);
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return RT_EOK;
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}
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static rt_err_t ccap_control(rt_device_t dev, int cmd, void *args)
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{
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nu_ccap_t psNuCcap = (nu_ccap_t)dev;
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rt_err_t ret = -RT_ERROR;
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if (psNuCcap == RT_NULL)
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goto exit_ccap_control;
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switch (cmd)
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{
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case CCAP_CMD_CONFIG:
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{
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ccap_config *psCcapConf = (ccap_config *)args;
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if (args == RT_NULL)
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goto exit_ccap_control;
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rt_memcpy(&psNuCcap->sConfig, psCcapConf, sizeof(ccap_config));
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}
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break;
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case CCAP_CMD_START_CAPTURE:
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/* Enable CCAP Interrupt */
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CCAP_EnableInt(psNuCcap->base, CCAP_INT_VIEN_Msk);
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/* Start capture engine */
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CCAP_Start(psNuCcap->base);
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break;
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case CCAP_CMD_STOP_CAPTURE:
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/* Disable CCAP Interrupt */
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CCAP_DisableInt(psNuCcap->base, CCAP_INT_VIEN_Msk);
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/* Stop capture engine */
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CCAP_Stop(psNuCcap->base, FALSE);
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break;
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case CCAP_CMD_SET_SENCLK:
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{
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rt_uint32_t u32SenClk;
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RT_ASSERT(args);
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u32SenClk = *((rt_uint32_t *)args);
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if (u32SenClk > 0)
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ccap_sensor_setfreq(psNuCcap, u32SenClk);
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}
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break;
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case CCAP_CMD_SET_PIPES:
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{
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ccap_view_info_t psViewInfo;
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RT_ASSERT(args);
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psViewInfo = (ccap_view_info_t)args;
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ret = ccap_pipe_configure(psNuCcap, psViewInfo);
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}
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break;
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case CCAP_CMD_SET_OPMODE:
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{
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RT_ASSERT(args);
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int i32IsOneSutterMode = *((int *)args);
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/* Set shutter or continuous mode */
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CCAP_SET_CTL(psNuCcap->base, (i32IsOneSutterMode > 0) ? CCAP_CTL_SHUTTER_Msk : 0);
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}
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break;
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case CCAP_CMD_SET_BASEADDR:
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{
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uint32_t u32Offset = 0;
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ccap_config_t psCcapConf;
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RT_ASSERT(args);
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psCcapConf = (ccap_config_t)args;
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/* Set System Memory Packet Base Address Register */
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CCAP_SetPacketBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Packet.pu8FarmAddr);
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/* Set System Memory Planar Y Base Address Register */
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CCAP_SetPlanarYBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset);
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u32Offset = psCcapConf->sPipeInfo_Planar.u32Height * psCcapConf->sPipeInfo_Planar.u32Width;
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/* Set System Memory Planar U Base Address Register */
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CCAP_SetPlanarUBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset);
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u32Offset += ((psCcapConf->sPipeInfo_Planar.u32Height * psCcapConf->sPipeInfo_Planar.u32Width) / 2);
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/* Set System Memory Planar V Base Address Register */
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CCAP_SetPlanarVBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset);
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}
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break;
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default:
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return -RT_ENOSYS;
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}
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ret = RT_EOK;
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exit_ccap_control:
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return ret;
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}
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#ifdef RT_USING_DEVICE_OPS
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static struct rt_device_ops ccap_ops =
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{
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.init = ccap_init,
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.open = ccap_open,
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.close = ccap_close,
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.read = RT_NULL,
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.write = RT_NULL,
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.control = ccap_control,
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};
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#endif
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static rt_err_t ccap_register(struct rt_device *device, const char *name, void *user_data)
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{
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RT_ASSERT(device);
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device->type = RT_Device_Class_Miscellaneous;
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device->rx_indicate = RT_NULL;
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device->tx_complete = RT_NULL;
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#ifdef RT_USING_DEVICE_OPS
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device->ops = &inputcapture_ops;
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#else
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device->init = ccap_init;
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device->open = ccap_open;
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device->close = ccap_close;
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device->read = RT_NULL;
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device->write = RT_NULL;
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device->control = ccap_control;
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#endif
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device->user_data = user_data;
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return rt_device_register(device, name, RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_STANDALONE);
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}
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/**
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* Hardware CCAP Initialization
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*/
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int rt_hw_ccap_init(void)
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{
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int i;
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rt_err_t ret = RT_EOK;
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for (i = (CCAP_START + 1); i < CCAP_CNT; i++)
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{
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rt_memset(&nu_ccap_arr[i].sConfig, 0, sizeof(ccap_config));
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ret = ccap_register(&nu_ccap_arr[i].device, nu_ccap_arr[i].name, NULL);
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RT_ASSERT(ret == RT_EOK);
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}
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return ret;
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}
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INIT_DEVICE_EXPORT(rt_hw_ccap_init);
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#endif
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