1107 lines
34 KiB
C
1107 lines
34 KiB
C
//*****************************************************************************
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//
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// i2c.c - Driver for Inter-IC (I2C) bus block.
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//
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// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup i2c_api
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_i2c.h"
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#include "inc/hw_ints.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_sysctl.h"
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#include "inc/hw_types.h"
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#include "driverlib/debug.h"
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#include "driverlib/i2c.h"
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#include "driverlib/interrupt.h"
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//*****************************************************************************
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//
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//! Initializes the I2C Master block.
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//!
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//! \param ulBase is the base address of the I2C Master module.
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//! \param ulI2CClk is the rate of the clock supplied to the I2C module.
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//! \param bFast set up for fast data transfers
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//!
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//! This function initializes operation of the I2C Master block. Upon
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//! successful initialization of the I2C block, this function will have set the
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//! bus speed for the master, and will have enabled the I2C Master block.
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//!
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//! If the parameter \e bFast is \b true, then the master block will be set up
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//! to transfer data at 400 kbps; otherwise, it will be set up to transfer data
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//! at 100 kbps.
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//!
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//! The peripheral clock will be the same as the processor clock. This will be
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//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
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//! if it is constant and known (to save the code/execution overhead of a call
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//! to SysCtlClockGet()).
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//!
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//! This function replaces the original I2CMasterInit() API and performs the
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//! same actions. A macro is provided in <tt>i2c.h</tt> to map the original
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//! API to this API.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk,
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tBoolean bFast)
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{
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unsigned long ulSCLFreq;
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unsigned long ulTPR;
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//
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// Check the arguments.
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//
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ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
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//
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// Must enable the device before doing anything else.
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//
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I2CMasterEnable(ulBase);
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//
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// Get the desired SCL speed.
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//
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if(bFast == true)
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{
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ulSCLFreq = 400000;
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}
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else
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{
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ulSCLFreq = 100000;
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}
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//
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// Compute the clock divider that achieves the fastest speed less than or
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// equal to the desired speed. The numerator is biased to favor a larger
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// clock divider so that the resulting clock is always less than or equal
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// to the desired clock, never greater.
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//
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ulTPR = ((ulI2CClk + (2 * 10 * ulSCLFreq) - 1) / (2 * 10 * ulSCLFreq)) - 1;
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HWREG(ulBase + I2C_O_MTPR) = ulTPR;
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}
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//*****************************************************************************
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//
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//! Initializes the I2C Slave block.
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//!
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//! \param ulBase is the base address of the I2C Slave module.
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//! \param ucSlaveAddr 7-bit slave address
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//!
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//! This function initializes operation of the I2C Slave block. Upon
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//! successful initialization of the I2C blocks, this function will have set
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//! the slave address and have enabled the I2C Slave block.
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//!
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//! The parameter \e ucSlaveAddr is the value that will be compared against the
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//! slave address sent by an I2C master.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
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ASSERT(!(ucSlaveAddr & 0x80));
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//
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// Must enable the device before doing anything else.
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//
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I2CSlaveEnable(ulBase);
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//
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// Set up the slave address.
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//
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HWREG(ulBase + I2C_O_SOAR) = ucSlaveAddr;
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}
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//*****************************************************************************
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//
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//! Enables the I2C Master block.
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//!
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//! \param ulBase is the base address of the I2C Master module.
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//!
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//! This will enable operation of the I2C Master block.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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I2CMasterEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
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//
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// Enable the master block.
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//
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HWREG(ulBase + I2C_O_MCR) |= I2C_MCR_MFE;
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}
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//*****************************************************************************
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//
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//! Enables the I2C Slave block.
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//!
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//! \param ulBase is the base address of the I2C Slave module.
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//!
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//! This will enable operation of the I2C Slave block.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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I2CSlaveEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
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//
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// Enable the clock to the slave block.
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//
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HWREG(ulBase - I2C0_SLAVE_BASE + I2C0_MASTER_BASE + I2C_O_MCR) |=
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I2C_MCR_SFE;
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//
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// Enable the slave.
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//
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HWREG(ulBase + I2C_O_SCSR) = I2C_SCSR_DA;
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}
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//*****************************************************************************
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//
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//! Disables the I2C master block.
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//!
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//! \param ulBase is the base address of the I2C Master module.
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//!
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//! This will disable operation of the I2C master block.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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I2CMasterDisable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
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//
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// Disable the master block.
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//
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HWREG(ulBase + I2C_O_MCR) &= ~(I2C_MCR_MFE);
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}
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//*****************************************************************************
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//
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//! Disables the I2C slave block.
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//!
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//! \param ulBase is the base address of the I2C Slave module.
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//!
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//! This will disable operation of the I2C slave block.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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I2CSlaveDisable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
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//
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// Disable the slave.
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//
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HWREG(ulBase + I2C_O_SCSR) = 0;
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//
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// Disable the clock to the slave block.
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//
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HWREG(ulBase - I2C0_SLAVE_BASE + I2C0_MASTER_BASE + I2C_O_MCR) &=
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~(I2C_MCR_SFE);
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}
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//*****************************************************************************
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//
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//! Registers an interrupt handler for the I2C module.
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//!
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//! \param ulBase is the base address of the I2C Master module.
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//! \param pfnHandler is a pointer to the function to be called when the
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//! I2C interrupt occurs.
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//!
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//! This sets the handler to be called when an I2C interrupt occurs. This will
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//! enable the global interrupt in the interrupt controller; specific I2C
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//! interrupts must be enabled via I2CMasterIntEnable() and
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//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's
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//! responsibility to clear the interrupt source via I2CMasterIntClear() and
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//! I2CSlaveIntClear().
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
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{
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unsigned long ulInt;
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//
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// Check the arguments.
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//
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ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
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//
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// Determine the interrupt number based on the I2C port.
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//
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ulInt = (ulBase == I2C0_MASTER_BASE) ? INT_I2C0 : INT_I2C1;
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//
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// Register the interrupt handler, returning an error if an error occurs.
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//
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IntRegister(ulInt, pfnHandler);
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//
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// Enable the I2C interrupt.
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//
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IntEnable(ulInt);
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}
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//*****************************************************************************
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//
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//! Unregisters an interrupt handler for the I2C module.
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//!
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//! \param ulBase is the base address of the I2C Master module.
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//!
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//! This function will clear the handler to be called when an I2C interrupt
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//! occurs. This will also mask off the interrupt in the interrupt controller
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//! so that the interrupt handler no longer is called.
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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I2CIntUnregister(unsigned long ulBase)
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{
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unsigned long ulInt;
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//
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// Check the arguments.
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//
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ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
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//
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// Determine the interrupt number based on the I2C port.
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//
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ulInt = (ulBase == I2C0_MASTER_BASE) ? INT_I2C0 : INT_I2C1;
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//
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// Disable the interrupt.
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//
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IntDisable(ulInt);
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//
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// Unregister the interrupt handler.
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//
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IntUnregister(ulInt);
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}
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//*****************************************************************************
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//
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//! Enables the I2C Master interrupt.
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//!
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//! \param ulBase is the base address of the I2C Master module.
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//!
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//! Enables the I2C Master interrupt source.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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I2CMasterIntEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
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//
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// Enable the master interrupt.
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//
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HWREG(ulBase + I2C_O_MIMR) = 1;
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}
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//*****************************************************************************
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//
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//! Enables the I2C Slave interrupt.
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//!
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//! \param ulBase is the base address of the I2C Slave module.
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//!
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//! Enables the I2C Slave interrupt source.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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I2CSlaveIntEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
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//
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// Enable the slave interrupt.
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//
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HWREG(ulBase + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA;
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}
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//*****************************************************************************
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//
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//! Enables individual I2C Slave interrupt sources.
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//!
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//! \param ulBase is the base address of the I2C Slave module.
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//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
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//!
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//! Enables the indicated I2C Slave interrupt sources. Only the sources that
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//! are enabled can be reflected to the processor interrupt; disabled sources
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//! have no effect on the processor.
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//!
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//! The \e ulIntFlags parameter is the logical OR of any of the following:
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//!
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//! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt
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//! - \b I2C_SLAVE_INT_START - Start condition detected interrupt
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//! - \b I2C_SLAVE_INT_DATA - Data interrupt
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
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//
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// Enable the slave interrupt.
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//
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HWREG(ulBase + I2C_O_SIMR) |= ulIntFlags;
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}
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//*****************************************************************************
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//
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//! Disables the I2C Master interrupt.
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//!
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//! \param ulBase is the base address of the I2C Master module.
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//!
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//! Disables the I2C Master interrupt source.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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I2CMasterIntDisable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
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//
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// Disable the master interrupt.
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//
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HWREG(ulBase + I2C_O_MIMR) = 0;
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}
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|
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//*****************************************************************************
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//
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//! Disables the I2C Slave interrupt.
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//!
|
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//! \param ulBase is the base address of the I2C Slave module.
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//!
|
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//! Disables the I2C Slave interrupt source.
|
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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I2CSlaveIntDisable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
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//
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// Disable the slave interrupt.
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//
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HWREG(ulBase + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA;
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}
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|
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//*****************************************************************************
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//
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//! Disables individual I2C Slave interrupt sources.
|
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//!
|
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//! \param ulBase is the base address of the I2C Slave module.
|
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//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
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//!
|
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//! Disables the indicated I2C Slave interrupt sources. Only the sources that
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//! are enabled can be reflected to the processor interrupt; disabled sources
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//! have no effect on the processor.
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//!
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//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
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//! parameter to I2CSlaveIntEnableEx().
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//!
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//! \return None.
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//
|
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//*****************************************************************************
|
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void
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I2CSlaveIntDisableEx(unsigned long ulBase, unsigned long ulIntFlags)
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{
|
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//
|
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// Check the arguments.
|
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//
|
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ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
|
|
|
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//
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// Disable the slave interrupt.
|
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//
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HWREG(ulBase + I2C_O_SIMR) &= ~ulIntFlags;
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}
|
|
|
|
//*****************************************************************************
|
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//
|
|
//! Gets the current I2C Master interrupt status.
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//!
|
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//! \param ulBase is the base address of the I2C Master module.
|
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//! \param bMasked is false if the raw interrupt status is requested and
|
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//! true if the masked interrupt status is requested.
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//!
|
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//! This returns the interrupt status for the I2C Master module. Either the
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//! raw interrupt status or the status of interrupts that are allowed to
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//! reflect to the processor can be returned.
|
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//!
|
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//! \return The current interrupt status, returned as \b true if active
|
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//! or \b false if not active.
|
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//
|
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//*****************************************************************************
|
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tBoolean
|
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I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked)
|
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{
|
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//
|
|
// Check the arguments.
|
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//
|
|
ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
|
|
|
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//
|
|
// Return either the interrupt status or the raw interrupt status as
|
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// requested.
|
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//
|
|
if(bMasked)
|
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{
|
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return((HWREG(ulBase + I2C_O_MMIS)) ? true : false);
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}
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else
|
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{
|
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return((HWREG(ulBase + I2C_O_MRIS)) ? true : false);
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the current I2C Slave interrupt status.
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Slave module.
|
|
//! \param bMasked is false if the raw interrupt status is requested and
|
|
//! true if the masked interrupt status is requested.
|
|
//!
|
|
//! This returns the interrupt status for the I2C Slave module. Either the raw
|
|
//! interrupt status or the status of interrupts that are allowed to reflect to
|
|
//! the processor can be returned.
|
|
//!
|
|
//! \return The current interrupt status, returned as \b true if active
|
|
//! or \b false if not active.
|
|
//
|
|
//*****************************************************************************
|
|
tBoolean
|
|
I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
|
|
|
|
//
|
|
// Return either the interrupt status or the raw interrupt status as
|
|
// requested.
|
|
//
|
|
if(bMasked)
|
|
{
|
|
return((HWREG(ulBase + I2C_O_SMIS)) ? true : false);
|
|
}
|
|
else
|
|
{
|
|
return((HWREG(ulBase + I2C_O_SRIS)) ? true : false);
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the current I2C Slave interrupt status.
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Slave module.
|
|
//! \param bMasked is false if the raw interrupt status is requested and
|
|
//! true if the masked interrupt status is requested.
|
|
//!
|
|
//! This returns the interrupt status for the I2C Slave module. Either the raw
|
|
//! interrupt status or the status of interrupts that are allowed to reflect to
|
|
//! the processor can be returned.
|
|
//!
|
|
//! \return Returns the current interrupt status, enumerated as a bit field of
|
|
//! values described in I2CSlaveIntEnableEx().
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
I2CSlaveIntStatusEx(unsigned long ulBase, tBoolean bMasked)
|
|
{
|
|
unsigned long ulValue;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
|
|
|
|
//
|
|
// Return either the interrupt status or the raw interrupt status as
|
|
// requested.
|
|
//
|
|
if(bMasked)
|
|
{
|
|
//
|
|
// Workaround for I2C slave masked interrupt status register errata
|
|
// (7.1) for Dustdevil Rev A0 devices.
|
|
//
|
|
if(CLASS_IS_DUSTDEVIL && REVISION_IS_A0)
|
|
{
|
|
ulValue = HWREG(ulBase + I2C_O_SRIS);
|
|
return(ulValue & HWREG(ulBase + I2C_O_SIMR));
|
|
}
|
|
else
|
|
{
|
|
return(HWREG(ulBase + I2C_O_SMIS));
|
|
}
|
|
}
|
|
else
|
|
{
|
|
return(HWREG(ulBase + I2C_O_SRIS));
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears I2C Master interrupt sources.
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Master module.
|
|
//!
|
|
//! The I2C Master interrupt source is cleared, so that it no longer asserts.
|
|
//! This must be done in the interrupt handler to keep it from being called
|
|
//! again immediately upon exit.
|
|
//!
|
|
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
|
|
//! several clock cycles before the interrupt source is actually cleared.
|
|
//! Therefore, it is recommended that the interrupt source be cleared early in
|
|
//! the interrupt handler (as opposed to the very last action) to avoid
|
|
//! returning from the interrupt handler before the interrupt source is
|
|
//! actually cleared. Failure to do so may result in the interrupt handler
|
|
//! being immediately reentered (since NVIC still sees the interrupt source
|
|
//! asserted).
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
I2CMasterIntClear(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
|
|
|
|
//
|
|
// Clear the I2C master interrupt source.
|
|
//
|
|
HWREG(ulBase + I2C_O_MICR) = I2C_MICR_IC;
|
|
|
|
//
|
|
// Workaround for I2C master interrupt clear errata for rev B Stellaris
|
|
// devices. For later devices, this write is ignored and therefore
|
|
// harmless (other than the slight performance hit).
|
|
//
|
|
HWREG(ulBase + I2C_O_MMIS) = I2C_MICR_IC;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears I2C Slave interrupt sources.
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Slave module.
|
|
//!
|
|
//! The I2C Slave interrupt source is cleared, so that it no longer asserts.
|
|
//! This must be done in the interrupt handler to keep it from being called
|
|
//! again immediately upon exit.
|
|
//!
|
|
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
|
|
//! several clock cycles before the interrupt source is actually cleared.
|
|
//! Therefore, it is recommended that the interrupt source be cleared early in
|
|
//! the interrupt handler (as opposed to the very last action) to avoid
|
|
//! returning from the interrupt handler before the interrupt source is
|
|
//! actually cleared. Failure to do so may result in the interrupt handler
|
|
//! being immediately reentered (since NVIC still sees the interrupt source
|
|
//! asserted).
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
I2CSlaveIntClear(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
|
|
|
|
//
|
|
// Clear the I2C slave interrupt source.
|
|
//
|
|
HWREG(ulBase + I2C_O_SICR) = I2C_SICR_DATAIC;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears I2C Slave interrupt sources.
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Slave module.
|
|
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
|
|
//!
|
|
//! The specified I2C Slave interrupt sources are cleared, so that they no
|
|
//! longer assert. This must be done in the interrupt handler to keep it from
|
|
//! being called again immediately upon exit.
|
|
//!
|
|
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
|
|
//! parameter to I2CSlaveIntEnableEx().
|
|
//!
|
|
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
|
|
//! several clock cycles before the interrupt source is actually cleared.
|
|
//! Therefore, it is recommended that the interrupt source be cleared early in
|
|
//! the interrupt handler (as opposed to the very last action) to avoid
|
|
//! returning from the interrupt handler before the interrupt source is
|
|
//! actually cleared. Failure to do so may result in the interrupt handler
|
|
//! being immediately reentered (since NVIC still sees the interrupt source
|
|
//! asserted).
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
|
|
|
|
//
|
|
// Clear the I2C slave interrupt source.
|
|
//
|
|
HWREG(ulBase + I2C_O_SICR) = ulIntFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Sets the address that the I2C Master will place on the bus.
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Master module.
|
|
//! \param ucSlaveAddr 7-bit slave address
|
|
//! \param bReceive flag indicating the type of communication with the slave
|
|
//!
|
|
//! This function will set the address that the I2C Master will place on the
|
|
//! bus when initiating a transaction. When the \e bReceive parameter is set
|
|
//! to \b true, the address will indicate that the I2C Master is initiating a
|
|
//! read from the slave; otherwise the address will indicate that the I2C
|
|
//! Master is initiating a write to the slave.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr,
|
|
tBoolean bReceive)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
|
|
ASSERT(!(ucSlaveAddr & 0x80));
|
|
|
|
//
|
|
// Set the address of the slave with which the master will communicate.
|
|
//
|
|
HWREG(ulBase + I2C_O_MSA) = (ucSlaveAddr << 1) | bReceive;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Indicates whether or not the I2C Master is busy.
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Master module.
|
|
//!
|
|
//! This function returns an indication of whether or not the I2C Master is
|
|
//! busy transmitting or receiving data.
|
|
//!
|
|
//! \return Returns \b true if the I2C Master is busy; otherwise, returns
|
|
//! \b false.
|
|
//
|
|
//*****************************************************************************
|
|
tBoolean
|
|
I2CMasterBusy(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
|
|
|
|
//
|
|
// Return the busy status.
|
|
//
|
|
if(HWREG(ulBase + I2C_O_MCS) & I2C_MCS_BUSY)
|
|
{
|
|
return(true);
|
|
}
|
|
else
|
|
{
|
|
return(false);
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Indicates whether or not the I2C bus is busy.
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Master module.
|
|
//!
|
|
//! This function returns an indication of whether or not the I2C bus is busy.
|
|
//! This function can be used in a multi-master environment to determine if
|
|
//! another master is currently using the bus.
|
|
//!
|
|
//! \return Returns \b true if the I2C bus is busy; otherwise, returns
|
|
//! \b false.
|
|
//
|
|
//*****************************************************************************
|
|
tBoolean
|
|
I2CMasterBusBusy(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
|
|
|
|
//
|
|
// Return the bus busy status.
|
|
//
|
|
if(HWREG(ulBase + I2C_O_MCS) & I2C_MCS_BUSBSY)
|
|
{
|
|
return(true);
|
|
}
|
|
else
|
|
{
|
|
return(false);
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Controls the state of the I2C Master module.
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Master module.
|
|
//! \param ulCmd command to be issued to the I2C Master module
|
|
//!
|
|
//! This function is used to control the state of the Master module send and
|
|
//! receive operations. The \e ucCmd parameter can be one of the following
|
|
//! values:
|
|
//!
|
|
//! - \b I2C_MASTER_CMD_SINGLE_SEND
|
|
//! - \b I2C_MASTER_CMD_SINGLE_RECEIVE
|
|
//! - \b I2C_MASTER_CMD_BURST_SEND_START
|
|
//! - \b I2C_MASTER_CMD_BURST_SEND_CONT
|
|
//! - \b I2C_MASTER_CMD_BURST_SEND_FINISH
|
|
//! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
|
|
//! - \b I2C_MASTER_CMD_BURST_RECEIVE_START
|
|
//! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT
|
|
//! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH
|
|
//! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
I2CMasterControl(unsigned long ulBase, unsigned long ulCmd)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
|
|
ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) ||
|
|
(ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_SEND_START) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
|
|
(ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP));
|
|
|
|
//
|
|
// Send the command.
|
|
//
|
|
HWREG(ulBase + I2C_O_MCS) = ulCmd;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the error status of the I2C Master module.
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Master module.
|
|
//!
|
|
//! This function is used to obtain the error status of the Master module send
|
|
//! and receive operations.
|
|
//!
|
|
//! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE,
|
|
//! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or
|
|
//! \b I2C_MASTER_ERR_ARB_LOST.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
I2CMasterErr(unsigned long ulBase)
|
|
{
|
|
unsigned long ulErr;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
|
|
|
|
//
|
|
// Get the raw error state
|
|
//
|
|
ulErr = HWREG(ulBase + I2C_O_MCS);
|
|
|
|
//
|
|
// If the I2C master is busy, then all the other bit are invalid, and
|
|
// don't have an error to report.
|
|
//
|
|
if(ulErr & I2C_MCS_BUSY)
|
|
{
|
|
return(I2C_MASTER_ERR_NONE);
|
|
}
|
|
|
|
//
|
|
// Check for errors.
|
|
//
|
|
if(ulErr & (I2C_MCS_ERROR | I2C_MCS_ARBLST))
|
|
{
|
|
return(ulErr & (I2C_MCS_ARBLST | I2C_MCS_DATACK | I2C_MCS_ADRACK));
|
|
}
|
|
else
|
|
{
|
|
return(I2C_MASTER_ERR_NONE);
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Transmits a byte from the I2C Master.
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Master module.
|
|
//! \param ucData data to be transmitted from the I2C Master
|
|
//!
|
|
//! This function will place the supplied data into I2C Master Data Register.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
I2CMasterDataPut(unsigned long ulBase, unsigned char ucData)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
|
|
|
|
//
|
|
// Write the byte.
|
|
//
|
|
HWREG(ulBase + I2C_O_MDR) = ucData;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Receives a byte that has been sent to the I2C Master.
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Master module.
|
|
//!
|
|
//! This function reads a byte of data from the I2C Master Data Register.
|
|
//!
|
|
//! \return Returns the byte received from by the I2C Master, cast as an
|
|
//! unsigned long.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
I2CMasterDataGet(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
|
|
|
|
//
|
|
// Read a byte.
|
|
//
|
|
return(HWREG(ulBase + I2C_O_MDR));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the I2C Slave module status
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Slave module.
|
|
//!
|
|
//! This function will return the action requested from a master, if any.
|
|
//! Possible values are:
|
|
//!
|
|
//! - \b I2C_SLAVE_ACT_NONE
|
|
//! - \b I2C_SLAVE_ACT_RREQ
|
|
//! - \b I2C_SLAVE_ACT_TREQ
|
|
//! - \b I2C_SLAVE_ACT_RREQ_FBR
|
|
//!
|
|
//! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been
|
|
//! requested of the I2C Slave module, \b I2C_SLAVE_ACT_RREQ to indicate that
|
|
//! an I2C master has sent data to the I2C Slave module, \b I2C_SLAVE_ACT_TREQ
|
|
//! to indicate that an I2C master has requested that the I2C Slave module send
|
|
//! data, and \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent
|
|
//! data to the I2C slave and the first byte following the slave's own address
|
|
//! has been received.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
I2CSlaveStatus(unsigned long ulBase)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
|
|
|
|
//
|
|
// Return the slave status.
|
|
//
|
|
return(HWREG(ulBase + I2C_O_SCSR));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Transmits a byte from the I2C Slave.
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Slave module.
|
|
//! \param ucData data to be transmitted from the I2C Slave
|
|
//!
|
|
//! This function will place the supplied data into I2C Slave Data Register.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
|
|
|
|
//
|
|
// Write the byte.
|
|
//
|
|
HWREG(ulBase + I2C_O_SDR) = ucData;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Receives a byte that has been sent to the I2C Slave.
|
|
//!
|
|
//! \param ulBase is the base address of the I2C Slave module.
|
|
//!
|
|
//! This function reads a byte of data from the I2C Slave Data Register.
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|
//!
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|
//! \return Returns the byte received from by the I2C Slave, cast as an
|
|
//! unsigned long.
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|
//
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|
//*****************************************************************************
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|
unsigned long
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|
I2CSlaveDataGet(unsigned long ulBase)
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|
{
|
|
//
|
|
// Check the arguments.
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|
//
|
|
ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
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|
|
|
//
|
|
// Read a byte.
|
|
//
|
|
return(HWREG(ulBase + I2C_O_SDR));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|