274 lines
6.9 KiB
C
274 lines
6.9 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-07-15 Magicoe The first version for LPC55S6x
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*/
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#include "rtdevice.h"
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#include "fsl_common.h"
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#include "fsl_iocon.h"
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#include "fsl_spi.h"
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#include "fsl_spi_dma.h"
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enum
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{
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#ifdef BSP_USING_SPI3
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SPI3_INDEX,
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#endif
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#ifdef BSP_USING_SPI8
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SPI8_INDEX,
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#endif
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};
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struct lpc_spi
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{
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struct rt_spi_bus parent;
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SPI_Type *SPIx;
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clock_attach_id_t clock_attach_id;
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clock_ip_name_t clock_name;
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DMA_Type *DMAx;
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uint8_t tx_dma_chl;
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uint8_t rx_dma_chl;
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dma_handle_t dma_tx_handle;
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dma_handle_t dma_rx_handle;
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spi_dma_handle_t spi_dma_handle;
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rt_sem_t sem;
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char *device_name;
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};
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static struct lpc_spi lpc_obj[] =
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{
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#ifdef BSP_USING_SPI3
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{
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.SPIx = SPI3,
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.clock_attach_id = kMAIN_CLK_to_FLEXCOMM3,
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.clock_name = kCLOCK_FlexComm3,
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.device_name = "spi3",
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.DMAx = DMA0,
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.tx_dma_chl = 9,
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.rx_dma_chl = 8,
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},
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#endif
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#ifdef BSP_USING_SPI8
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{
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.SPIx = SPI8,
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.clock_attach_id = kMAIN_CLK_to_HSLSPI,
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.clock_name = kCLOCK_Hs_Lspi,
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.device_name = "spi8",
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.DMAx = DMA0,
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.tx_dma_chl = 3,
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.rx_dma_chl = 2,
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},
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#endif
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};
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static uint32_t lpc_get_spi_freq(SPI_Type *base)
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{
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uint32_t freq = 0;
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if(base == SPI3)
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{
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freq = CLOCK_GetFlexCommClkFreq(kCLOCK_FlexComm3);
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}
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if(base == SPI8)
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{
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freq = CLOCK_GetFlexCommClkFreq(kCLOCK_Hs_Lspi);
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}
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return freq;
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}
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static rt_err_t lpc_spi_init(SPI_Type *base, struct rt_spi_configuration *cfg)
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{
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spi_master_config_t masterConfig = {0};
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SPI_MasterGetDefaultConfig(&masterConfig);
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if(cfg->data_width != 8 && cfg->data_width != 16)
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{
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cfg->data_width = 8;
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}
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masterConfig.baudRate_Bps = cfg->max_hz;
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if(cfg->data_width == 8)
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{
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masterConfig.dataWidth = kSPI_Data8Bits;
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}
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else if(cfg->data_width == 16)
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{
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masterConfig.dataWidth = kSPI_Data16Bits;
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}
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if(cfg->mode & RT_SPI_MSB)
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{
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masterConfig.direction = kSPI_MsbFirst;
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}
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else
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{
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masterConfig.direction = kSPI_LsbFirst;
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}
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if(cfg->mode & RT_SPI_CPHA)
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{
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masterConfig.phase = kSPI_ClockPhaseSecondEdge;
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}
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else
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{
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masterConfig.phase = kSPI_ClockPhaseFirstEdge;
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}
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if(cfg->mode & RT_SPI_CPOL)
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{
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masterConfig.polarity = kSPI_ClockPolarityActiveLow;
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}
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else
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{
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masterConfig.polarity = kSPI_ClockPolarityActiveHigh;
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}
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SPI_MasterInit(base, &masterConfig, lpc_get_spi_freq(base));
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return RT_EOK;
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}
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rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
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{
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rt_err_t ret = RT_EOK;
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struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
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ret = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL);
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return ret;
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}
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static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
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{
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rt_err_t ret = RT_EOK;
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struct lpc_spi *spi = rt_container_of(device->bus, struct lpc_spi, parent);
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ret = lpc_spi_init(spi->SPIx, cfg);
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return ret;
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}
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static void SPI_MasterUserCallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData)
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{
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struct lpc_spi *spi = (struct lpc_spi*)userData;
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rt_sem_release(spi->sem);
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}
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static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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int i;
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spi_transfer_t transfer = {0};
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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struct lpc_spi *spi = rt_container_of(device->bus, struct lpc_spi, parent);
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if(message->cs_take && (device->cs_pin != PIN_NONE))
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{
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rt_pin_write(device->cs_pin, PIN_LOW);
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}
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transfer.dataSize = message->length;
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transfer.rxData = (uint8_t *)(message->recv_buf);
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transfer.txData = (uint8_t *)(message->send_buf);
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transfer.configFlags = kSPI_FrameAssert;
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// if(message->length < MAX_DMA_TRANSFER_SIZE)
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if(0)
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{
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SPI_MasterTransferBlocking(spi->SPIx, &transfer);
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}
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else
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{
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uint32_t block, remain;
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block = message->length / DMA_MAX_TRANSFER_COUNT;
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remain = message->length % DMA_MAX_TRANSFER_COUNT;
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for(i=0; i<block; i++)
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{
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transfer.dataSize = DMA_MAX_TRANSFER_COUNT;
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if(message->recv_buf) transfer.rxData = (uint8_t *)(message->recv_buf + i*DMA_MAX_TRANSFER_COUNT);
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if(message->send_buf) transfer.txData = (uint8_t *)(message->send_buf + i*DMA_MAX_TRANSFER_COUNT);
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SPI_MasterTransferDMA(spi->SPIx, &spi->spi_dma_handle, &transfer);
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rt_sem_take(spi->sem, RT_WAITING_FOREVER);
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}
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if(remain)
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{
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transfer.dataSize = remain;
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if(message->recv_buf) transfer.rxData = (uint8_t *)(message->recv_buf + i*DMA_MAX_TRANSFER_COUNT);
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if(message->send_buf) transfer.txData = (uint8_t *)(message->send_buf + i*DMA_MAX_TRANSFER_COUNT);
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SPI_MasterTransferDMA(spi->SPIx, &spi->spi_dma_handle, &transfer);
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rt_sem_take(spi->sem, RT_WAITING_FOREVER);
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}
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}
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if(message->cs_release && (device->cs_pin != PIN_NONE))
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{
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rt_pin_write(device->cs_pin, PIN_HIGH);
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}
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return message->length;
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}
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static struct rt_spi_ops lpc_spi_ops =
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{
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.configure = spi_configure,
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.xfer = spixfer
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};
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int rt_hw_spi_init(void)
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{
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int i;
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for(i=0; i<ARRAY_SIZE(lpc_obj); i++)
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{
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CLOCK_AttachClk(lpc_obj[i].clock_attach_id);
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lpc_obj[i].parent.parent.user_data = &lpc_obj[i];
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lpc_obj[i].sem = rt_sem_create("sem_spi", 0, RT_IPC_FLAG_FIFO);
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DMA_EnableChannel(lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl);
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DMA_EnableChannel(lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl);
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DMA_SetChannelPriority(lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl, kDMA_ChannelPriority3);
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DMA_SetChannelPriority(lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl, kDMA_ChannelPriority2);
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DMA_CreateHandle(&lpc_obj[i].dma_tx_handle, lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl);
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DMA_CreateHandle(&lpc_obj[i].dma_rx_handle, lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl);
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SPI_MasterTransferCreateHandleDMA(lpc_obj[i].SPIx, &lpc_obj[i].spi_dma_handle, SPI_MasterUserCallback, &lpc_obj[i], &lpc_obj[i].dma_tx_handle, &lpc_obj[i].dma_rx_handle);
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rt_spi_bus_register(&lpc_obj[i].parent, lpc_obj[i].device_name, &lpc_spi_ops);
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}
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return RT_EOK;
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}
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INIT_DEVICE_EXPORT(rt_hw_spi_init);
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