372 lines
9.3 KiB
C
372 lines
9.3 KiB
C
/**
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* @file lp.c
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* @brief Low power functions
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*/
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/* ****************************************************************************
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* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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* $Date: 2019-10-07 11:05:30 -0500 (Mon, 07 Oct 2019) $
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* $Revision: 47429 $
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*
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*************************************************************************** */
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/***** Includes *****/
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#include "lp.h"
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#include "pwrseq_regs.h"
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#include "mxc_errors.h"
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#include "gcr_regs.h"
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#include "mxc_config.h"
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#include "mxc_sys.h"
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#include "flc.h"
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#include "tmr_utils.h"
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/***** Functions *****/
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void LP_ClearWakeStatus(void)
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{
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MXC_PWRSEQ->lp_wakefl = 0xFFFFFFFF;
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/* These flags are slow to clear, so block until they do */
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while(MXC_PWRSEQ->lp_wakefl & (MXC_PWRSEQ->lpwk_en));
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}
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void LP_EnableSRAM3(void)
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{
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MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF;
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}
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void LP_DisableSRAM3(void)
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{
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MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF;
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}
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void LP_EnableSRAM2(void)
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{
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MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF;
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}
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void LP_DisableSRAM2(void)
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{
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MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF;
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}
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void LP_EnableSRAM1(void)
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{
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MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF;
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}
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void LP_DisableSRAM1(void)
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{
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MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF;
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}
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void LP_EnableSRAM0(void)
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{
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MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF;
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}
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void LP_DisableSRAM0(void)
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{
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MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF;
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}
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void LP_EnableICacheLightSleep(void)
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{
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MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_ICACHELS);
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}
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void LP_DisableICacheLightSleep(void)
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{
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MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_ICACHELS);
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}
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void LP_EnableSysRAM3LightSleep(void)
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{
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MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM3LS);
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}
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void LP_DisableSysRAM3LightSleep(void)
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{
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MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM3LS);
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}
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void LP_EnableSysRAM2LightSleep(void)
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{
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MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM2LS);
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}
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void LP_DisableSysRAM2LightSleep(void)
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{
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MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM2LS);
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}
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void LP_EnableSysRAM1LightSleep(void)
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{
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MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM1LS);
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}
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void LP_DisableSysRAM1LightSleep(void)
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{
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MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM1LS);
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}
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void LP_EnableSysRAM0LightSleep(void)
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{
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MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM0LS);
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}
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void LP_DisableSysRAM0LightSleep(void)
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{
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MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM0LS);
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}
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void LP_EnableRTCAlarmWakeup(void)
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{
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MXC_GCR->pm |= MXC_F_GCR_PM_RTCWKEN;
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}
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void LP_DisableRTCAlarmWakeup(void)
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{
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MXC_GCR->pm &= ~MXC_F_GCR_PM_RTCWKEN;
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}
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void LP_EnableGPIOWakeup(const gpio_cfg_t *wu_pins)
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{
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MXC_GCR->pm |= MXC_F_GCR_PM_GPIOWKEN;
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switch(wu_pins->port)
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{
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case 0: MXC_PWRSEQ->lpwk_en |= wu_pins->mask; break;
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}
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}
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void LP_DisableGPIOWakeup(const gpio_cfg_t *wu_pins)
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{
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switch(wu_pins->port)
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{
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case 0: MXC_PWRSEQ->lpwk_en &= ~wu_pins->mask; break;
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}
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if(MXC_PWRSEQ->lpwk_en == 0)
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{
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MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIOWKEN;
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}
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}
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void LP_EnterSleepMode(void)
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{
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// Clear SLEEPDEEP bit
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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// Go into Sleep mode and wait for an interrupt to wake the processor
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__WFI();
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}
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void LP_EnterDeepSleepMode(void)
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{
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// Set SLEEPDEEP bit
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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// Auto-powerdown 96 MHz oscillator when in deep sleep
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MXC_GCR->pm |= MXC_F_GCR_PM_HIRCPD;
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// Go into Deepsleep mode and wait for an interrupt to wake the processor
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__WFI();
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}
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void LP_EnterBackupMode(void)
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{
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MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
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MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP;
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while(1);
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}
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void LP_EnterShutdownMode(void)
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{
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MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
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MXC_GCR->pm |= MXC_S_GCR_PM_MODE_SHUTDOWN;
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while(1);
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}
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void LP_SetOperatingVoltage(lp_ovr_t ovr)
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{
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uint32_t div;
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//Set flash wait state for any clock so its not to low after clock changes.
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MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x5UL << MXC_F_GCR_MEMCKCN_FWS_POS);
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//set the OVR bits
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MXC_PWRSEQ->lp_ctrl &= ~(MXC_F_PWRSEQ_LP_CTRL_OVR);
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MXC_PWRSEQ->lp_ctrl |= ovr;
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//Set LVE bit
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if(ovr == LP_OVR_0_9){
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MXC_FLC->cn |= MXC_F_FLC_CN_LVE;
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}
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else{
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MXC_FLC->cn &= ~(MXC_F_FLC_CN_LVE);
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}
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// Update SystemCoreClock variable
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SystemCoreClockUpdate();
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// Get the clock divider
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div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS;
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//Set Flash Wait States
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if(ovr == LP_OVR_0_9){
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if(div == 0){
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MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
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} else{
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MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
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}
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} else if( ovr == LP_OVR_1_0){
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if(div == 0){
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MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
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} else{
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MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
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}
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} else {
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if(div == 0){
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MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x4UL << MXC_F_GCR_MEMCKCN_FWS_POS);
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} else if(div == 1){
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MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
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} else{
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MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
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}
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}
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}
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void LP_EnableSRamRet0(void){
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MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0;
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}
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void LP_DisableSRamRet0(void){
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MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0;
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}
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void LP_EnableSRamRet1(void){
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MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1;
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}
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void LP_DisableSRamRet1(void){
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MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1;
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}
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void LP_EnableSRamRet2(void){
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MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2;
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}
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void LP_DisableSRamRet2(void){
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MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2;
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}
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void LP_EnableSRamRet3(void){
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MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3;
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}
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void LP_DisableSRamRet3(void){
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MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3;
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}
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void LP_EnableBlockDetect(void){
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MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS;
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}
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void LP_DisableBlockDetect(void){
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MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS;
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}
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void LP_EnableRamRetReg(void){
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MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RETREG_EN;
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}
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void LP_DisableRamRetReg(void){
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MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RETREG_EN;
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}
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void LP_EnableFastWk(void){
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MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN;
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}
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void LP_DisableFastWk(void){
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MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN;
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}
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void LP_EnableBandGap(void){
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MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_BG_OFF;
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}
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void LP_DisableBandGap(void){
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MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_BG_OFF;
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}
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void LP_EnableVCorePORSignal(void){
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MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS;
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}
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void LP_DisableVCorePORSignal(void){
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MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS;
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}
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void LP_EnableLDO(void){
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MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_LDO_DIS;
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}
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void LP_DisableLDO(void){
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MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_LDO_DIS;
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}
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void LP_EnableVCoreSVM(void){
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MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS;
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}
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void LP_DisableVCoreSVM(void){
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MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS;
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}
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void LP_EnableVDDIOPorMonitoF(void){
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MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS;
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}
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void LP_DisableVDDIOPorMonitor(void){
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MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS;
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}
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