90 lines
1.8 KiB
C
90 lines
1.8 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2011-09-15 Bernard first version
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* 2018-11-22 Jesven add rt_hw_cpu_id()
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <board.h>
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#ifdef RT_USING_SMP
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int rt_hw_cpu_id(void)
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{
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int cpu_id;
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__asm__ volatile (
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"mrc p15, 0, %0, c0, c0, 5"
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:"=r"(cpu_id)
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);
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cpu_id &= 0xf;
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return cpu_id;
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};
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void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
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{
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lock->slock = 0;
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}
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void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
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{
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unsigned long tmp;
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unsigned long newval;
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rt_hw_spinlock_t lockval;
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__asm__ __volatile__(
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"pld [%0]"
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::"r"(&lock->slock)
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);
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__asm__ __volatile__(
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"1: ldrex %0, [%3]\n"
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" add %1, %0, %4\n"
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" strex %2, %1, [%3]\n"
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" teq %2, #0\n"
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" bne 1b"
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: "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
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: "r" (&lock->slock), "I" (1 << 16)
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: "cc");
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while (lockval.tickets.next != lockval.tickets.owner) {
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__asm__ __volatile__("wfe":::"memory");
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lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
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}
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__asm__ volatile ("dmb":::"memory");
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}
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void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
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{
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__asm__ volatile ("dmb":::"memory");
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lock->tickets.owner++;
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__asm__ volatile ("dsb ishst\nsev":::"memory");
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}
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#endif /*RT_USING_SMP*/
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/**
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* @addtogroup ARM CPU
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*/
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/*@{*/
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/** shutdown CPU */
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RT_WEAK void rt_hw_cpu_shutdown()
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{
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rt_uint32_t level;
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rt_kprintf("shutdown...\n");
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level = rt_hw_interrupt_disable();
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while (level)
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{
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RT_ASSERT(0);
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}
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}
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/*@}*/
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