ecf2d82159
* Synchronize the code of the rt mart branch to the master branch.
* TTY device
* Add lwP code from rt-smart
* Add vnode in DFS, but DFS will be re-write for rt-smart
* There are three libcpu for rt-smart:
* arm/cortex-a, arm/aarch64
* riscv64
Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>
60 lines
1.3 KiB
C
60 lines
1.3 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/28 Bernard The unify RISC-V porting code.
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <encoding.h>
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#include "sbi.h"
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static volatile uint64_t time_elapsed = 0;
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static volatile unsigned long tick_cycles = 0;
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static uint64_t get_ticks()
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{
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__asm__ __volatile__(
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"rdtime %0"
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: "=r"(time_elapsed));
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return time_elapsed;
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}
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int tick_isr(void)
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{
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// uint64_t core_id = current_coreid();
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int tick_cycles = 40000;
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// clint->mtimecmp[core_id] += tick_cycles;
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rt_tick_increase();
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sbi_set_timer(get_ticks() + tick_cycles);
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return 0;
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}
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/* Sets and enable the timer interrupt */
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int rt_hw_tick_init(void)
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{
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/* Read core id */
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// unsigned long core_id = current_coreid();
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unsigned long interval = 1000/RT_TICK_PER_SECOND;
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/* Clear the Supervisor-Timer bit in SIE */
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clear_csr(sie, SIP_STIP);
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/* calculate the tick cycles */
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// tick_cycles = interval * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / CLINT_CLOCK_DIV / 1000ULL - 1;
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tick_cycles = 40000;
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/* Set timer */
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sbi_set_timer(get_ticks() + tick_cycles);
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/* Enable the Supervisor-Timer bit in SIE */
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set_csr(sie, SIP_STIP);
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return 0;
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}
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