421 lines
23 KiB
C
421 lines
23 KiB
C
/*
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* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* $Date: 14. Nov 2017
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* $Revision: V2.3
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*
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* Project: NAND Flash Driver definitions
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*/
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/* History:
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* Version 2.3
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* Extended ARM_NAND_ECC_INFO structure
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* Version 2.2
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* ARM_NAND_STATUS made volatile
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* Version 2.1
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* Updated ARM_NAND_ECC_INFO structure and ARM_NAND_ECC_xxx definitions
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* Version 2.0
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* New simplified driver:
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* complexity moved to upper layer (command agnostic)
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* Added support for:
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* NV-DDR & NV-DDR2 Interface (ONFI specification)
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* VCC, VCCQ and VPP Power Supply Control
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* WP (Write Protect) Control
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* Version 1.11
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* Changed prefix ARM_DRV -> ARM_DRIVER
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* Version 1.10
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* Namespace prefix ARM_ added
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* Version 1.00
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* Initial release
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*/
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#ifndef DRIVER_NAND_H_
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#define DRIVER_NAND_H_
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "Driver_Common.h"
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#define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */
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/****** NAND Device Power *****/
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#define ARM_NAND_POWER_VCC_Pos 0
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#define ARM_NAND_POWER_VCC_Msk (0x07UL << ARM_NAND_POWER_VCC_Pos)
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#define ARM_NAND_POWER_VCC_OFF (0x01UL << ARM_NAND_POWER_VCC_Pos) ///< VCC Power off
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#define ARM_NAND_POWER_VCC_3V3 (0x02UL << ARM_NAND_POWER_VCC_Pos) ///< VCC = 3.3V
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#define ARM_NAND_POWER_VCC_1V8 (0x03UL << ARM_NAND_POWER_VCC_Pos) ///< VCC = 1.8V
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#define ARM_NAND_POWER_VCCQ_Pos 3
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#define ARM_NAND_POWER_VCCQ_Msk (0x07UL << ARM_NAND_POWER_VCCQ_Pos)
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#define ARM_NAND_POWER_VCCQ_OFF (0x01UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ I/O Power off
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#define ARM_NAND_POWER_VCCQ_3V3 (0x02UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 3.3V
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#define ARM_NAND_POWER_VCCQ_1V8 (0x03UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 1.8V
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#define ARM_NAND_POWER_VPP_OFF (1UL << 6) ///< VPP off
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#define ARM_NAND_POWER_VPP_ON (1Ul << 7) ///< VPP on
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/****** NAND Control Codes *****/
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#define ARM_NAND_BUS_MODE (0x01) ///< Set Bus Mode as specified with arg
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#define ARM_NAND_BUS_DATA_WIDTH (0x02) ///< Set Bus Data Width as specified with arg
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#define ARM_NAND_DRIVER_STRENGTH (0x03) ///< Set Driver Strength as specified with arg
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#define ARM_NAND_DEVICE_READY_EVENT (0x04) ///< Generate \ref ARM_NAND_EVENT_DEVICE_READY; arg: 0=disabled (default), 1=enabled
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#define ARM_NAND_DRIVER_READY_EVENT (0x05) ///< Generate \ref ARM_NAND_EVENT_DRIVER_READY; arg: 0=disabled (default), 1=enabled
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/*----- NAND Bus Mode (ONFI - Open NAND Flash Interface) -----*/
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#define ARM_NAND_BUS_INTERFACE_Pos 4
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#define ARM_NAND_BUS_INTERFACE_Msk (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)
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#define ARM_NAND_BUS_SDR (0x00UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: SDR (Single Data Rate) - Traditional interface (default)
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#define ARM_NAND_BUS_DDR (0x01UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: NV-DDR (Double Data Rate)
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#define ARM_NAND_BUS_DDR2 (0x02UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: NV-DDR2 (Double Data Rate)
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#define ARM_NAND_BUS_TIMING_MODE_Pos 0
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#define ARM_NAND_BUS_TIMING_MODE_Msk (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)
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#define ARM_NAND_BUS_TIMING_MODE_0 (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 0 (default)
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#define ARM_NAND_BUS_TIMING_MODE_1 (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 1
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#define ARM_NAND_BUS_TIMING_MODE_2 (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 2
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#define ARM_NAND_BUS_TIMING_MODE_3 (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 3
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#define ARM_NAND_BUS_TIMING_MODE_4 (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 4 (SDR EDO capable)
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#define ARM_NAND_BUS_TIMING_MODE_5 (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 5 (SDR EDO capable)
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#define ARM_NAND_BUS_TIMING_MODE_6 (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 6 (NV-DDR2 only)
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#define ARM_NAND_BUS_TIMING_MODE_7 (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 7 (NV-DDR2 only)
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#define ARM_NAND_BUS_DDR2_DO_WCYC_Pos 8
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#define ARM_NAND_BUS_DDR2_DO_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)
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#define ARM_NAND_BUS_DDR2_DO_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 0 (default)
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#define ARM_NAND_BUS_DDR2_DO_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 1
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#define ARM_NAND_BUS_DDR2_DO_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 2
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#define ARM_NAND_BUS_DDR2_DO_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 4
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#define ARM_NAND_BUS_DDR2_DI_WCYC_Pos 12
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#define ARM_NAND_BUS_DDR2_DI_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)
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#define ARM_NAND_BUS_DDR2_DI_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 0 (default)
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#define ARM_NAND_BUS_DDR2_DI_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 1
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#define ARM_NAND_BUS_DDR2_DI_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 2
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#define ARM_NAND_BUS_DDR2_DI_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 4
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#define ARM_NAND_BUS_DDR2_VEN (1UL << 16) ///< DDR2 Enable external VREFQ as reference
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#define ARM_NAND_BUS_DDR2_CMPD (1UL << 17) ///< DDR2 Enable complementary DQS (DQS_c) signal
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#define ARM_NAND_BUS_DDR2_CMPR (1UL << 18) ///< DDR2 Enable complementary RE_n (RE_c) signal
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/*----- NAND Data Bus Width -----*/
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#define ARM_NAND_BUS_DATA_WIDTH_8 (0x00) ///< Bus Data Width: 8 bit (default)
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#define ARM_NAND_BUS_DATA_WIDTH_16 (0x01) ///< Bus Data Width: 16 bit
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/*----- NAND Driver Strength (ONFI - Open NAND Flash Interface) -----*/
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#define ARM_NAND_DRIVER_STRENGTH_18 (0x00) ///< Driver Strength 2.0x = 18 Ohms
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#define ARM_NAND_DRIVER_STRENGTH_25 (0x01) ///< Driver Strength 1.4x = 25 Ohms
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#define ARM_NAND_DRIVER_STRENGTH_35 (0x02) ///< Driver Strength 1.0x = 35 Ohms (default)
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#define ARM_NAND_DRIVER_STRENGTH_50 (0x03) ///< Driver Strength 0.7x = 50 Ohms
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/****** NAND ECC for Read/Write Data Mode and Sequence Execution Code *****/
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#define ARM_NAND_ECC_INDEX_Pos 0
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#define ARM_NAND_ECC_INDEX_Msk (0xFFUL << ARM_NAND_ECC_INDEX_Pos)
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#define ARM_NAND_ECC(n) ((n) & ARM_NAND_ECC_INDEX_Msk) ///< Select ECC
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#define ARM_NAND_ECC0 (1UL << 8) ///< Use ECC0 of selected ECC
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#define ARM_NAND_ECC1 (1UL << 9) ///< Use ECC1 of selected ECC
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/****** NAND Flag for Read/Write Data Mode and Sequence Execution Code *****/
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#define ARM_NAND_DRIVER_DONE_EVENT (1UL << 16) ///< Generate \ref ARM_NAND_EVENT_DRIVER_DONE
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/****** NAND Sequence Execution Code *****/
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#define ARM_NAND_CODE_SEND_CMD1 (1UL << 17) ///< Send Command 1
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#define ARM_NAND_CODE_SEND_ADDR_COL1 (1UL << 18) ///< Send Column Address 1
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#define ARM_NAND_CODE_SEND_ADDR_COL2 (1UL << 19) ///< Send Column Address 2
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#define ARM_NAND_CODE_SEND_ADDR_ROW1 (1UL << 20) ///< Send Row Address 1
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#define ARM_NAND_CODE_SEND_ADDR_ROW2 (1UL << 21) ///< Send Row Address 2
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#define ARM_NAND_CODE_SEND_ADDR_ROW3 (1UL << 22) ///< Send Row Address 3
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#define ARM_NAND_CODE_INC_ADDR_ROW (1UL << 23) ///< Auto-increment Row Address
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#define ARM_NAND_CODE_WRITE_DATA (1UL << 24) ///< Write Data
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#define ARM_NAND_CODE_SEND_CMD2 (1UL << 25) ///< Send Command 2
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#define ARM_NAND_CODE_WAIT_BUSY (1UL << 26) ///< Wait while R/Bn busy
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#define ARM_NAND_CODE_READ_DATA (1UL << 27) ///< Read Data
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#define ARM_NAND_CODE_SEND_CMD3 (1UL << 28) ///< Send Command 3
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#define ARM_NAND_CODE_READ_STATUS (1UL << 29) ///< Read Status byte and check FAIL bit (bit 0)
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/*----- NAND Sequence Execution Code: Command -----*/
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#define ARM_NAND_CODE_CMD1_Pos 0
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#define ARM_NAND_CODE_CMD1_Msk (0xFFUL << ARM_NAND_CODE_CMD1_Pos)
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#define ARM_NAND_CODE_CMD2_Pos 8
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#define ARM_NAND_CODE_CMD2_Msk (0xFFUL << ARM_NAND_CODE_CMD2_Pos)
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#define ARM_NAND_CODE_CMD3_Pos 16
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#define ARM_NAND_CODE_CMD3_Msk (0xFFUL << ARM_NAND_CODE_CMD3_Pos)
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/*----- NAND Sequence Execution Code: Column Address -----*/
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#define ARM_NAND_CODE_ADDR_COL1_Pos 0
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#define ARM_NAND_CODE_ADDR_COL1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)
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#define ARM_NAND_CODE_ADDR_COL2_Pos 8
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#define ARM_NAND_CODE_ADDR_COL2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)
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/*----- NAND Sequence Execution Code: Row Address -----*/
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#define ARM_NAND_CODE_ADDR_ROW1_Pos 0
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#define ARM_NAND_CODE_ADDR_ROW1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)
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#define ARM_NAND_CODE_ADDR_ROW2_Pos 8
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#define ARM_NAND_CODE_ADDR_ROW2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)
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#define ARM_NAND_CODE_ADDR_ROW3_Pos 16
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#define ARM_NAND_CODE_ADDR_ROW3_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)
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/****** NAND specific error codes *****/
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#define ARM_NAND_ERROR_ECC (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< ECC generation/correction failed
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/**
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\brief NAND ECC (Error Correction Code) Information
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*/
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typedef struct _ARM_NAND_ECC_INFO {
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uint32_t type : 2; ///< Type: 1=ECC0 over Main, 2=ECC0 over Main+Spare, 3=ECC0 over Main and ECC1 over Spare
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uint32_t page_layout : 1; ///< Page layout: 0=|Main0|Spare0|...|MainN-1|SpareN-1|, 1=|Main0|...|MainN-1|Spare0|...|SpareN-1|
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uint32_t page_count : 3; ///< Number of virtual pages: N = 2 ^ page_count
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uint32_t page_size : 4; ///< Virtual Page size (Main+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448, 15=Not used (extended description)
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uint32_t reserved : 14; ///< Reserved (must be zero)
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uint32_t correctable_bits : 8; ///< Number of correctable bits (based on 512 byte codeword size)
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uint16_t codeword_size [2]; ///< Number of bytes over which ECC is calculated
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uint16_t ecc_size [2]; ///< ECC size in bytes (rounded up)
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uint16_t ecc_offset [2]; ///< ECC offset in bytes (where ECC starts in Spare)
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/* Extended description */
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uint16_t virtual_page_size [2]; ///< Virtual Page size in bytes (Main/Spare)
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uint16_t codeword_offset [2]; ///< Codeword offset in bytes (where ECC protected data starts in Main/Spare)
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uint16_t codeword_gap [2]; ///< Codeword gap in bytes till next protected data
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uint16_t ecc_gap [2]; ///< ECC gap in bytes till next generated ECC
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} ARM_NAND_ECC_INFO;
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/**
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\brief NAND Status
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*/
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typedef volatile struct _ARM_NAND_STATUS {
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uint32_t busy : 1; ///< Driver busy flag
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uint32_t ecc_error : 1; ///< ECC error detected (cleared on next Read/WriteData or ExecuteSequence)
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uint32_t reserved : 30;
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} ARM_NAND_STATUS;
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/****** NAND Event *****/
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#define ARM_NAND_EVENT_DEVICE_READY (1UL << 0) ///< Device Ready: R/Bn rising edge
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#define ARM_NAND_EVENT_DRIVER_READY (1UL << 1) ///< Driver Ready
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#define ARM_NAND_EVENT_DRIVER_DONE (1UL << 2) ///< Driver operation done
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#define ARM_NAND_EVENT_ECC_ERROR (1UL << 3) ///< ECC could not correct data
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// Function documentation
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/**
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\fn ARM_DRIVER_VERSION ARM_NAND_GetVersion (void)
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\brief Get driver version.
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\return \ref ARM_DRIVER_VERSION
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*/
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/**
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\fn ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void)
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\brief Get driver capabilities.
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\return \ref ARM_NAND_CAPABILITIES
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*/
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/**
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\fn int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event)
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\brief Initialize the NAND Interface.
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\param[in] cb_event Pointer to \ref ARM_NAND_SignalEvent
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\return \ref execution_status
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*/
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/**
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\fn int32_t ARM_NAND_Uninitialize (void)
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\brief De-initialize the NAND Interface.
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\return \ref execution_status
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*/
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/**
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\fn int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state)
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\brief Control the NAND interface power.
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\param[in] state Power state
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\return \ref execution_status
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*/
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/**
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\fn int32_t ARM_NAND_DevicePower (uint32_t voltage)
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\brief Set device power supply voltage.
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\param[in] voltage NAND Device supply voltage
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\return \ref execution_status
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*/
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/**
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\fn int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable)
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\brief Control WPn (Write Protect).
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\param[in] dev_num Device number
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\param[in] enable
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- \b false Write Protect off
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- \b true Write Protect on
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\return \ref execution_status
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*/
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/**
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\fn int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable)
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\brief Control CEn (Chip Enable).
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\param[in] dev_num Device number
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\param[in] enable
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- \b false Chip Enable off
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- \b true Chip Enable on
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\return \ref execution_status
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*/
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/**
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\fn int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num)
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\brief Get Device Busy pin state.
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\param[in] dev_num Device number
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\return 1=busy, 0=not busy, or error
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*/
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/**
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\fn int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd)
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\brief Send command to NAND device.
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\param[in] dev_num Device number
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\param[in] cmd Command
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\return \ref execution_status
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*/
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/**
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\fn int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr)
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\brief Send address to NAND device.
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\param[in] dev_num Device number
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\param[in] addr Address
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\return \ref execution_status
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*/
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/**
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\fn int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode)
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\brief Read data from NAND device.
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\param[in] dev_num Device number
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\param[out] data Pointer to buffer for data to read from NAND device
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\param[in] cnt Number of data items to read
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\param[in] mode Operation mode
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\return number of data items read or \ref execution_status
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*/
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/**
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\fn int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode)
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\brief Write data to NAND device.
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\param[in] dev_num Device number
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\param[out] data Pointer to buffer with data to write to NAND device
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\param[in] cnt Number of data items to write
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\param[in] mode Operation mode
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\return number of data items written or \ref execution_status
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*/
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/**
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\fn int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,
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uint32_t addr_col, uint32_t addr_row,
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void *data, uint32_t data_cnt,
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uint8_t *status, uint32_t *count)
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\brief Execute sequence of operations.
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\param[in] dev_num Device number
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\param[in] code Sequence code
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\param[in] cmd Command(s)
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\param[in] addr_col Column address
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\param[in] addr_row Row address
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\param[in,out] data Pointer to data to be written or read
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\param[in] data_cnt Number of data items in one iteration
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\param[out] status Pointer to status read
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\param[in,out] count Number of iterations
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\return \ref execution_status
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*/
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/**
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\fn int32_t ARM_NAND_AbortSequence (uint32_t dev_num)
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\brief Abort sequence execution.
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\param[in] dev_num Device number
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\return \ref execution_status
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*/
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/**
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\fn int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg)
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\brief Control NAND Interface.
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\param[in] dev_num Device number
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\param[in] control Operation
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\param[in] arg Argument of operation
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\return \ref execution_status
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*/
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/**
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\fn ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num)
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\brief Get NAND status.
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\param[in] dev_num Device number
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\return NAND status \ref ARM_NAND_STATUS
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*/
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/**
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\fn int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info)
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\brief Inquire about available ECC.
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\param[in] index Inquire ECC index
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\param[out] info Pointer to ECC information \ref ARM_NAND_ECC_INFO retrieved
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\return \ref execution_status
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*/
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/**
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\fn void ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event)
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\brief Signal NAND event.
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\param[in] dev_num Device number
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\param[in] event Event notification mask
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\return none
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*/
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typedef void (*ARM_NAND_SignalEvent_t) (uint32_t dev_num, uint32_t event); ///< Pointer to \ref ARM_NAND_SignalEvent : Signal NAND Event.
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/**
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\brief NAND Driver Capabilities.
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*/
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typedef struct _ARM_NAND_CAPABILITIES {
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uint32_t event_device_ready : 1; ///< Signal Device Ready event (R/Bn rising edge)
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uint32_t reentrant_operation : 1; ///< Supports re-entrant operation (SendCommand/Address, Read/WriteData)
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uint32_t sequence_operation : 1; ///< Supports Sequence operation (ExecuteSequence, AbortSequence)
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uint32_t vcc : 1; ///< Supports VCC Power Supply Control
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uint32_t vcc_1v8 : 1; ///< Supports 1.8 VCC Power Supply
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uint32_t vccq : 1; ///< Supports VCCQ I/O Power Supply Control
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uint32_t vccq_1v8 : 1; ///< Supports 1.8 VCCQ I/O Power Supply
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uint32_t vpp : 1; ///< Supports VPP High Voltage Power Supply Control
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uint32_t wp : 1; ///< Supports WPn (Write Protect) Control
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uint32_t ce_lines : 4; ///< Number of CEn (Chip Enable) lines: ce_lines + 1
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uint32_t ce_manual : 1; ///< Supports manual CEn (Chip Enable) Control
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uint32_t rb_monitor : 1; ///< Supports R/Bn (Ready/Busy) Monitoring
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uint32_t data_width_16 : 1; ///< Supports 16-bit data
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uint32_t ddr : 1; ///< Supports NV-DDR Data Interface (ONFI)
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uint32_t ddr2 : 1; ///< Supports NV-DDR2 Data Interface (ONFI)
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uint32_t sdr_timing_mode : 3; ///< Fastest (highest) SDR Timing Mode supported (ONFI)
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uint32_t ddr_timing_mode : 3; ///< Fastest (highest) NV_DDR Timing Mode supported (ONFI)
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uint32_t ddr2_timing_mode : 3; ///< Fastest (highest) NV_DDR2 Timing Mode supported (ONFI)
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uint32_t driver_strength_18 : 1; ///< Supports Driver Strength 2.0x = 18 Ohms
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uint32_t driver_strength_25 : 1; ///< Supports Driver Strength 1.4x = 25 Ohms
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uint32_t driver_strength_50 : 1; ///< Supports Driver Strength 0.7x = 50 Ohms
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uint32_t reserved : 2; ///< Reserved (must be zero)
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} ARM_NAND_CAPABILITIES;
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/**
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\brief Access structure of the NAND Driver.
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*/
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typedef struct _ARM_DRIVER_NAND {
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ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_NAND_GetVersion : Get driver version.
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ARM_NAND_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_NAND_GetCapabilities : Get driver capabilities.
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int32_t (*Initialize) (ARM_NAND_SignalEvent_t cb_event); ///< Pointer to \ref ARM_NAND_Initialize : Initialize NAND Interface.
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int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_NAND_Uninitialize : De-initialize NAND Interface.
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int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_NAND_PowerControl : Control NAND Interface Power.
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int32_t (*DevicePower) (uint32_t voltage); ///< Pointer to \ref ARM_NAND_DevicePower : Set device power supply voltage.
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int32_t (*WriteProtect) (uint32_t dev_num, bool enable); ///< Pointer to \ref ARM_NAND_WriteProtect : Control WPn (Write Protect).
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int32_t (*ChipEnable) (uint32_t dev_num, bool enable); ///< Pointer to \ref ARM_NAND_ChipEnable : Control CEn (Chip Enable).
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int32_t (*GetDeviceBusy) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_GetDeviceBusy : Get Device Busy pin state.
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int32_t (*SendCommand) (uint32_t dev_num, uint8_t cmd); ///< Pointer to \ref ARM_NAND_SendCommand : Send command to NAND device.
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int32_t (*SendAddress) (uint32_t dev_num, uint8_t addr); ///< Pointer to \ref ARM_NAND_SendAddress : Send address to NAND device.
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int32_t (*ReadData) (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode); ///< Pointer to \ref ARM_NAND_ReadData : Read data from NAND device.
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int32_t (*WriteData) (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode); ///< Pointer to \ref ARM_NAND_WriteData : Write data to NAND device.
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int32_t (*ExecuteSequence)(uint32_t dev_num, uint32_t code, uint32_t cmd,
|
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uint32_t addr_col, uint32_t addr_row,
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void *data, uint32_t data_cnt,
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uint8_t *status, uint32_t *count); ///< Pointer to \ref ARM_NAND_ExecuteSequence : Execute sequence of operations.
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int32_t (*AbortSequence) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_AbortSequence : Abort sequence execution.
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int32_t (*Control) (uint32_t dev_num, uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_NAND_Control : Control NAND Interface.
|
|
ARM_NAND_STATUS (*GetStatus) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_GetStatus : Get NAND status.
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|
int32_t (*InquireECC) ( int32_t index, ARM_NAND_ECC_INFO *info); ///< Pointer to \ref ARM_NAND_InquireECC : Inquire about available ECC.
|
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} const ARM_DRIVER_NAND;
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|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
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|
#endif /* DRIVER_NAND_H_ */
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