108 lines
3.1 KiB
NASM
108 lines
3.1 KiB
NASM
;
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; Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
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;
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; SPDX-License-Identifier: Apache-2.0
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;
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; Change Logs:
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; Date Author Notes
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; 2021-11-16 Dystopia the first version
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;
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;-----------------------------------------------------------
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; build thread stack for C6000 DSP
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;-----------------------------------------------------------
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;-----------------------------------------------------------
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; macro definition
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;-----------------------------------------------------------
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ADDRESS_MSK .set 0xFFFFFFF0
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;
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;-----------------------------------------------------------
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;
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.sect ".text"
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;
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;-----------------------------------------------------------
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;
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;
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; rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
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; tentry --> A4
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; parameter --> B4
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; stack_addr --> A6
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; texit --> B6
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;{
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.global rt_hw_stack_init
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rt_hw_stack_init:
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SUB A6,1,B1 ;
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MVKL .S1 ADDRESS_MSK,A1 ;
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MVKH .S1 ADDRESS_MSK,A1 ; Build address mask
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MVC .S2 CSR,B0 ;
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AND -2,B0,B0 ; Clear GIE bit
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OR 2,B0,B0 ; Set PGIE bit for interrupt return
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AND A1,B1,B1 ; Ensure alignment
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;
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; Actually build the stack frame.
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;
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MV .S1 B1,A3
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MV .S1 B14,A2
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STDW .D2T1 A3:A2,*--B1[1] ; Initial B15:B14
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SUBAW .D2 B1,2,B1
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ZERO A2
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ZERO A3 ; Clear value
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A15:A14
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A13:A12
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A11:A10
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A9:A8
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A7:A6
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MV .S1 B4,A2
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A5:A4
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ZERO A2
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A3:A2
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A1:A0
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A31:A30
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A29:A28
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A27:A26
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A25:A24
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A23:A22
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A21:A20
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A19:A18
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STDW .D2T1 A3:A2,*B1--[1] ; Initial A17:A16
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B13:B12
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B11:B10
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B9:B8
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B7:B6
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B5:B4
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MV .S1 B6,A3
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B3:B2
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ZERO A3
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B1:B0
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B31:B30
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B29:B28
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B27:B26
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B25:B24
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B23:B22
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B21:B20
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B19:B18
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STDW .D2T1 A3:A2,*B1--[1] ; Initial B17:B16
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MV .S1 A4,A3
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MV .S1 B0,A2
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STDW .D2T1 A3:A2,*B1--[1] ; Initial PC:CSR
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ZERO A2
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ZERO A3
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STDW .D2T1 A3:A2,*B1--[1] ; Initial ILC:RILC
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B B3
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MVKL .S2 0x3,B0
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MV .S1 B0,A3
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MVKL .S1 1,A2
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STDW .D2T1 A3:A2,*B1--[1] ; Initial TSR:stack type
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MV .S1 B1,A4 ; Save to TCB
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;}
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.end
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