166 lines
4.2 KiB
ArmAsm
166 lines
4.2 KiB
ArmAsm
/*
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* File : context_vdsp.S
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2012-02-13 mojingxian First version
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*/
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.global _rt_hw_interrupt_disable;
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.global _rt_hw_interrupt_enable;
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.global _interrupt_thread_switch;
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.extern _rt_interrupt_from_thread;
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.extern _rt_interrupt_to_thread;
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.extern _rt_thread_switch_interrupt_flag;
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.section/DOUBLE64 program;
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/*
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* rt_base_t rt_hw_interrupt_disable();
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* return value in R0.
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*/
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_rt_hw_interrupt_disable:
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CLI R0;
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_rt_hw_interrupt_disable.end:
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NOP;
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NOP;
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NOP;
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RTS;
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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* R0->level
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*/
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_rt_hw_interrupt_enable:
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STI R0;
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_rt_hw_interrupt_enable.end:
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NOP;
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NOP;
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NOP;
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RTS;
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_interrupt_thread_switch:
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/* Save context, interrupts disabled by IPEND[4] bit */
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[ -- SP ] = R0;
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[ -- SP ] = P1;
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[ -- SP ] = RETS;
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[ -- SP ] = R1;
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[ -- SP ] = R2;
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[ -- SP ] = P0;
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[ -- SP ] = P2;
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[ -- SP ] = ASTAT;
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R1 = RETI; /* IPEND[4] is currently set, globally disabling interrupts */
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/* IPEND[4] will stay set when RETI is saved through R1 */
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[ -- SP ] = R1;
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[ -- SP ] = (R7:3, P5:3);
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[ -- SP ] = FP;
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[ -- SP ] = I0;
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[ -- SP ] = I1;
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[ -- SP ] = I2;
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[ -- SP ] = I3;
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[ -- SP ] = B0;
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[ -- SP ] = B1;
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[ -- SP ] = B2;
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[ -- SP ] = B3;
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[ -- SP ] = L0;
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[ -- SP ] = L1;
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[ -- SP ] = L2;
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[ -- SP ] = L3;
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[ -- SP ] = M0;
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[ -- SP ] = M1;
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[ -- SP ] = M2;
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[ -- SP ] = M3;
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R1.L = A0.x;
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[ -- SP ] = R1;
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R1 = A0.w;
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[ -- SP ] = R1;
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R1.L = A1.x;
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[ -- SP ] = R1;
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R1 = A1.w;
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[ -- SP ] = R1;
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[ -- SP ] = LC0;
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R3 = 0;
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LC0 = R3;
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[ -- SP ] = LC1;
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R3 = 0;
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LC1 = R3;
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[ -- SP ] = LT0;
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[ -- SP ] = LT1;
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[ -- SP ] = LB0;
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[ -- SP ] = LB1;
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/* Context save done so save SP in the TCB */
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P1.h = _rt_interrupt_from_thread;
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P1.l = _rt_interrupt_from_thread;
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P2 = [ P1 ];
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[ P2 ] = SP;
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/* clear rt_thread_switch_interrupt_flag to 0 */
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P1.h = _rt_thread_switch_interrupt_flag;
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P1.l = _rt_thread_switch_interrupt_flag;
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R0 = 0;
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[ P1 ] = R0;
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/* Get a pointer to the high ready task's TCB */
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P1.h = _rt_interrupt_to_thread;
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P1.l = _rt_interrupt_to_thread;
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P2 = [ P1 ];
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SP = [ P2 ];
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/* Restoring CPU context and return to task */
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LB1 = [ SP ++ ];
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LB0 = [ SP ++ ];
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LT1 = [ SP ++ ];
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LT0 = [ SP ++ ];
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LC1 = [ SP ++ ];
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LC0 = [ SP ++ ];
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R0 = [ SP ++ ];
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A1 = R0;
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R0 = [ SP ++ ];
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A1.x = R0.L;
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R0 = [ SP ++ ];
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A0 = R0;
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R0 = [ SP ++ ];
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A0.x = R0.L;
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M3 = [ SP ++ ];
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M2 = [ SP ++ ];
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M1 = [ SP ++ ];
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M0 = [ SP ++ ];
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L3 = [ SP ++ ];
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L2 = [ SP ++ ];
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L1 = [ SP ++ ];
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L0 = [ SP ++ ];
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B3 = [ SP ++ ];
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B2 = [ SP ++ ];
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B1 = [ SP ++ ];
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B0 = [ SP ++ ];
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I3 = [ SP ++ ];
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I2 = [ SP ++ ];
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I1 = [ SP ++ ];
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I0 = [ SP ++ ];
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FP = [ SP ++ ];
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(R7:3, P5:3) = [ SP ++ ];
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RETI = [ SP ++ ]; /* IPEND[4] will stay set when RETI popped from stack */
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ASTAT = [ SP ++ ];
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P2 = [ SP ++ ];
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P0 = [ SP ++ ];
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R2 = [ SP ++ ];
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R1 = [ SP ++ ];
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RETS = [ SP ++ ];
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P1 = [ SP ++ ];
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R0 = [ SP ++ ];
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_interrupt_thread_switch.end:
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RTI;
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