345 lines
9.9 KiB
C
345 lines
9.9 KiB
C
/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-12-12 Wayne First version
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*
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******************************************************************************/
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#include <rtconfig.h>
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#if (defined(BSP_USING_GPIO) && defined(RT_USING_PIN))
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#include <rtdevice.h>
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#include <rthw.h>
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#include "NuMicro.h"
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#include <nu_bitutil.h>
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#include <drv_gpio.h>
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#include <stdlib.h>
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#include <drv_sys.h>
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/* Private define ---------------------------------------------------------------*/
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#define PORT_OFFSET 0x40
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#define IRQ_MAX_NUM 16 //Max support 32
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/* Private functions ------------------------------------------------------------*/
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static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode);
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static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value);
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static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin);
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static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args);
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static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin);
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static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled);
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static rt_base_t nu_gpio_pin_get(const char *name);
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/* Private variables ------------------------------------------------------------*/
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[IRQ_MAX_NUM];
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static struct rt_pin_ops nu_gpio_ops =
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{
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nu_gpio_mode,
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nu_gpio_write,
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nu_gpio_read,
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nu_gpio_attach_irq,
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nu_gpio_detach_irq,
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nu_gpio_irq_enable,
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nu_gpio_pin_get,
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};
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static IRQn_Type au32GPIRQ[NU_PORT_CNT] = {IRQ_GPA, IRQ_GPB, IRQ_GPC, IRQ_GPD, IRQ_GPE, IRQ_GPF, IRQ_GPG};
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static rt_uint32_t g_u32PinIrqMask = 0x0;
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/* Functions define ------------------------------------------------------------*/
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static rt_err_t nu_port_check(rt_int32_t pin)
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{
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if (NU_GET_PORT(pin) >= NU_PORT_CNT)
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return -(RT_ERROR);
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return RT_EOK;
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}
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static rt_int32_t nu_find_irqindex(rt_uint32_t pin_index)
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{
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rt_int32_t irqindex;
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rt_int32_t u32PinIrqStatus = g_u32PinIrqMask;
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// Find index of pin is attached in pool.
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while ((irqindex = nu_ctz(u32PinIrqStatus)) < IRQ_MAX_NUM) // Count Trailing Zeros ==> Find First One
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{
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if (pin_irq_hdr_tab[irqindex].pin == pin_index)
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return irqindex;
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u32PinIrqStatus &= ~(1 << irqindex);
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}
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return -(RT_ERROR);
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}
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static void pin_irq_hdr(rt_uint32_t irq_status, rt_uint32_t port_index)
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{
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rt_int32_t irqindex, i;
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rt_int32_t pinindex = port_index * GPIO_PIN_MAX ;
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while ((i = nu_ctz(irq_status)) < GPIO_PIN_MAX)// Count Trailing Zeros ==> Find First One
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{
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int pin_mask = (1 << i);
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irqindex = nu_find_irqindex(pinindex + i);
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if (irqindex != -(RT_ERROR))
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{
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if (pin_irq_hdr_tab[irqindex].hdr)
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{
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pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args);
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}
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}
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// Clear the served bit.
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irq_status &= ~pin_mask;
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}
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}
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static rt_base_t nu_gpio_pin_get(const char *name)
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{
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/* Get pin number by name,such as PA.0, PF12 */
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if ((name[2] == '\0') || ((name[2] == '.') && (name[3] == '\0')))
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return -(RT_EINVAL);
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long number;
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if ((name[2] == '.'))
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number = atol(&name[3]);
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else
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number = atol(&name[2]);
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if (number > 15)
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return -(RT_EINVAL);
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if (name[1] >= 'A' && name[1] <= 'H')
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return ((name[1] - 'A') * 0x10) + number;
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if (name[1] >= 'a' && name[1] <= 'h')
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return ((name[1] - 'a') * 0x10) + number;
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return -(RT_EINVAL);
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}
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static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
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{
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GPIO_T *PORT;
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if (nu_port_check(pin))
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return;
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PORT = (GPIO_T *)(PA_BA + (NU_GET_PORT(pin) * PORT_OFFSET));
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if (mode == PIN_MODE_INPUT_PULLUP)
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{
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GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT);
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GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_PULL_UP);
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT);
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GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_PULL_DOWN);
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}
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else if (mode == PIN_MODE_OUTPUT)
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{
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GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_OUTPUT);
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}
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else if (mode == PIN_MODE_INPUT)
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{
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GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT);
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GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_DISABLE);
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}
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else if (mode == PIN_MODE_OUTPUT_OD)
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{
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GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_OPEN_DRAIN);
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GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_DISABLE);
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}
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}
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static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
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{
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if (nu_port_check(pin))
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return;
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GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)) = value;
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}
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static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin)
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{
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if (nu_port_check(pin))
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return PIN_LOW;
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return GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin));
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}
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static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args)
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{
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rt_base_t level;
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rt_int32_t irqindex;
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if (nu_port_check(pin))
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return -(RT_ERROR);
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level = rt_hw_interrupt_disable();
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// Find index of pin is attached in pool.
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if ((irqindex = nu_find_irqindex(pin)) >= 0)
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goto exit_nu_gpio_attach_irq;
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// Find available index of pin in pool.
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if ((irqindex = nu_cto(g_u32PinIrqMask)) < IRQ_MAX_NUM) // Count Trailing Ones ==> Find First Zero
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goto exit_nu_gpio_attach_irq;
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rt_hw_interrupt_enable(level);
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return -(RT_EBUSY);
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exit_nu_gpio_attach_irq:
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pin_irq_hdr_tab[irqindex].pin = pin;
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pin_irq_hdr_tab[irqindex].hdr = hdr;
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pin_irq_hdr_tab[irqindex].mode = mode;
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pin_irq_hdr_tab[irqindex].args = args;
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g_u32PinIrqMask |= (1 << irqindex);
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin)
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{
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rt_base_t level;
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rt_int32_t irqindex;
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rt_int32_t u32PinIrqStatus;
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if (nu_port_check(pin))
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return -(RT_ERROR);
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level = rt_hw_interrupt_disable();
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u32PinIrqStatus = g_u32PinIrqMask;
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// Find index of pin is attached in pool.
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while ((irqindex = nu_ctz(u32PinIrqStatus)) < IRQ_MAX_NUM)// Count Trailing Zeros ==> Find First One
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{
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if (pin_irq_hdr_tab[irqindex].pin == pin)
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{
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pin_irq_hdr_tab[irqindex].pin = PIN_IRQ_PIN_NONE;
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pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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pin_irq_hdr_tab[irqindex].mode = PIN_IRQ_MODE_RISING;
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pin_irq_hdr_tab[irqindex].args = RT_NULL;
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g_u32PinIrqMask &= ~(1 << irqindex);
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break;
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}
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u32PinIrqStatus &= ~(1 << irqindex);
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}
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static void nu_gpio_isr(int vector, void *param)
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{
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rt_uint32_t int_status;
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GPIO_T *PORT = (GPIO_T *)param;
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rt_uint32_t port_idx = ((rt_uint32_t)PORT - PA_BA) / PORT_OFFSET ;
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int_status = PORT->INTSRC;
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pin_irq_hdr(int_status, port_idx);
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PORT->INTSRC = int_status;
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}
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static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
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{
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GPIO_T *PORT;
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rt_base_t level;
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uint32_t u32IntAttribs;
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rt_int32_t irqindex;
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rt_err_t ret = RT_EOK;
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IRQn_Type irqn;
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if (nu_port_check(pin))
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return -(RT_ERROR);
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level = rt_hw_interrupt_disable();
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irqindex = nu_find_irqindex(pin);
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if (irqindex == -(RT_ERROR))
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{
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ret = -RT_ERROR;
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goto exit_nu_gpio_irq_enable;
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}
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PORT = (GPIO_T *)(PA_BA + (NU_GET_PORT(pin) * PORT_OFFSET));
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irqn = au32GPIRQ[NU_GET_PORT(pin)];
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if (enabled == PIN_IRQ_ENABLE)
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{
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if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING)
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u32IntAttribs = GPIO_INT_RISING;
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else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_FALLING)
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u32IntAttribs = GPIO_INT_FALLING;
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else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING_FALLING)
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u32IntAttribs = GPIO_INT_BOTH_EDGE;
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else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_HIGH_LEVEL)
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u32IntAttribs = GPIO_INT_HIGH;
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else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_LOW_LEVEL)
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u32IntAttribs = GPIO_INT_LOW;
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else
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goto exit_nu_gpio_irq_enable;
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GPIO_EnableInt(PORT, NU_GET_PINS(pin), u32IntAttribs);
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rt_hw_interrupt_umask(irqn);
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}
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else
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{
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GPIO_DisableInt(PORT, NU_GET_PINS(pin));
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rt_hw_interrupt_mask(irqn);
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}
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exit_nu_gpio_irq_enable:
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rt_hw_interrupt_enable(level);
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return -(ret);
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}
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int rt_hw_gpio_init(void)
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{
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char szTmp[16];
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int i;
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rt_int32_t irqindex;
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for (irqindex = 0; irqindex < IRQ_MAX_NUM ; irqindex++)
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{
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pin_irq_hdr_tab[irqindex].pin = PIN_IRQ_PIN_NONE;
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pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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pin_irq_hdr_tab[irqindex].mode = PIN_IRQ_MODE_RISING;
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pin_irq_hdr_tab[irqindex].args = RT_NULL;
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}
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for (i = 0; i < NU_PORT_CNT ; i++)
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{
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IRQn_Type irqn = au32GPIRQ[i];
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snprintf(szTmp, sizeof(szTmp), "gpio-%d", i);
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rt_hw_interrupt_install(irqn, nu_gpio_isr, (void *)(PA_BA + (i * PORT_OFFSET)), szTmp);
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rt_hw_interrupt_set_type(irqn, HIGH_LEVEL_SENSITIVE);
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}
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nu_sys_ipclk_enable(GPIOCKEN);
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return rt_device_pin_register("gpio", &nu_gpio_ops, RT_NULL);
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}
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INIT_BOARD_EXPORT(rt_hw_gpio_init);
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#endif //#if (defined(BSP_USING_GPIO) && defined(RT_USING_PIN))
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