624 lines
16 KiB
C
624 lines
16 KiB
C
/*
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* Copyright (c) 2021 hpmicro
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef HPM_INTERRUPT_H
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#define HPM_INTERRUPT_H
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#include "riscv/riscv_core.h"
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#include "hpm_common.h"
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#include "hpm_plic_drv.h"
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/**
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* @brief INTERRUPT driver APIs
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* @defgroup irq_interface INTERRUPT driver APIs
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* @{
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*/
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#define M_MODE 0 /*!< Machine mode */
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#define S_MODE 1 /*!< Supervisor mode */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Enable global IRQ with mask
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*
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* @param[in] mask interrupt mask to be enabaled
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*/
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ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask)
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{
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set_csr(CSR_MSTATUS, mask);
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}
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/**
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* @brief Disable global IRQ with mask
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*
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* @param[in] mask interrupt mask to be disabled
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*/
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ATTR_ALWAYS_INLINE static inline void disable_global_irq(uint32_t mask)
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{
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clear_csr(CSR_MSTATUS, mask);
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}
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/**
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* @brief Enable IRQ from interrupt controller
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*
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*/
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ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void)
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{
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set_csr(CSR_MIE, CSR_MIE_MEIE_MASK);
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}
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/**
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* @brief Disable IRQ from interrupt controller
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*
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*/
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ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void)
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{
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clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK);
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}
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/**
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* @brief Enable machine timer IRQ
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*/
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ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void)
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{
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set_csr(CSR_MIE, CSR_MIE_MTIE_MASK);
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}
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/**
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* @brief Disable machine timer IRQ
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*
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*/
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ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void)
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{
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clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK);
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}
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/*
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* CPU Machine SWI control
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*
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* Machine SWI (MSIP) is connected to PLICSW irq 1.
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*/
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#define PLICSWI 1
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/**
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* @brief Initialize software interrupt
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*
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*/
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ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void)
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{
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__plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI);
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}
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/**
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* @brief Enable software interrupt
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*
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*/
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ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void)
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{
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set_csr(CSR_MIE, CSR_MIE_MSIE_MASK);
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}
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/**
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* @brief Disable software interrupt
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*
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*/
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ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void)
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{
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clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK);
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}
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/**
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* @brief Trigger software interrupt
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*
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*/
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ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void)
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{
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__plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI);
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}
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/**
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* @brief Claim software interrupt
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*
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*/
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ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void)
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{
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__plic_claim_irq(HPM_PLICSW_BASE, 0);
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}
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/**
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* @brief Complete software interrupt
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*
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*/
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ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void)
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{
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__plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI);
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}
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/*
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* @brief Enable IRQ for machine mode
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*
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* @param[in] irq Interrupt number
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*/
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#define intc_m_enable_irq(irq) \
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intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq)
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/*
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* @brief Disable IRQ for machine mode
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*
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* @param[in] irq Interrupt number
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*/
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#define intc_m_disable_irq(irq) \
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intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq)
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#define intc_m_set_threshold(threshold) \
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intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold)
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/*
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* @brief Complete IRQ for machine mode
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*
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* @param[in] irq Interrupt number
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*/
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#define intc_m_complete_irq(irq) \
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intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq)
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/*
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* @brief Claim IRQ for machine mode
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*
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*/
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#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE)
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/*
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* @brief Enable IRQ for machine mode with priority
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*
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* @param[in] irq Interrupt number
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* @param[in] priority Priority of interrupt
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*/
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#define intc_m_enable_irq_with_priority(irq, priority) \
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do { \
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intc_set_irq_priority(irq, priority); \
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intc_m_enable_irq(irq); \
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} while(0);
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/*
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* @brief Enable specific interrupt
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*
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* @param[in] target Target to handle specific interrupt
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* @param[in] irq Interrupt number
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*/
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ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq)
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{
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__plic_enable_irq(HPM_PLIC_BASE, target, irq);
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}
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/**
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* @brief Set interrupt priority
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*
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* @param[in] irq Interrupt number
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* @param[in] priority Priority of interrupt
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*/
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ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority)
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{
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__plic_set_irq_priority(HPM_PLIC_BASE, irq, priority);
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}
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/**
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* @brief Disable specific interrupt
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*
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* @param[in] target Target to handle specific interrupt
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* @param[in] irq Interrupt number
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*/
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ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq)
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{
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__plic_disable_irq(HPM_PLIC_BASE, target, irq);
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}
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/**
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* @brief Set interrupt threshold
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*
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* @param[in] target Target to handle specific interrupt
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* @param[in] threshold Threshold of IRQ can be serviced
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*/
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ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold)
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{
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__plic_set_threshold(HPM_PLIC_BASE, target, threshold);
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}
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/**
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* @brief Claim IRQ
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*
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* @param[in] target Target to handle specific interrupt
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*
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*/
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ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target)
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{
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return __plic_claim_irq(HPM_PLIC_BASE, target);
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}
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/**
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* @brief Complete IRQ
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*
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* @param[in] target Target to handle specific interrupt
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* @param[in] irq Specific IRQ to be completed
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*
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*/
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ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq)
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{
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__plic_complete_irq(HPM_PLIC_BASE, target, irq);
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}
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/*
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* Vectored based irq install and uninstall
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*/
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extern int __vector_table[];
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extern void default_irq_entry(void);
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/**
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* @brief Install ISR for certain IRQ for ram based vector table
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*
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* @param[in] irq Target interrupt number
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* @param[in] isr Interrupt service routine
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*
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*/
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ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr)
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{
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__vector_table[irq] = isr;
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}
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/**
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* @brief Uninstall ISR for certain IRQ for ram based vector table
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*
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* @param[in] irq Target interrupt number
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*
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*/
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ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq)
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{
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__vector_table[irq] = (int)default_irq_entry;
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}
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/*
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* Inline nested irq entry/exit macros
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*/
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/*
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* @brief Save CSR
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* @param[in] r Target CSR to be saved
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*/
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#define SAVE_CSR(r) register long __##r = read_csr(r);
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/*
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* @brief Restore macro
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*
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* @param[in] r Target CSR to be restored
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*/
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#define RESTORE_CSR(r) write_csr(r, __##r);
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#if SUPPORT_PFT_ARCH
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#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS)
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#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS)
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#else
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#define SAVE_MXSTATUS()
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#define RESTORE_MXSTATUS()
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#endif
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#ifdef __riscv_flen
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#define SAVE_FCSR() register int __fcsr = read_fcsr();
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#define RESTORE_FCSR() write_fcsr(__fcsr);
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#else
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#define SAVE_FCSR()
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#define RESTORE_FCSR()
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#endif
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#ifdef __riscv_dsp
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#define SAVE_UCODE() SAVE_CSR(CSR_UCODE)
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#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE)
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#else
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#define SAVE_UCODE()
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#define RESTORE_UCODE()
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#endif
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#ifdef __riscv_flen
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/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP) + 21 FPU caller registers */
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#define CONTEXT_REG_NUM (4*(16 + 4 + 1 + 21))
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#else
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/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP)*/
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#define CONTEXT_REG_NUM (4*(16 + 4 + 1))
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#endif
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#ifdef __riscv_flen
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/*
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* Save FPU caller registers:
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* NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 21 in the stack
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*/
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#define SAVE_FPU_CONTEXT() { \
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__asm volatile("fsw ft0, 21*4(sp) \n\
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fsw ft1, 22*4(sp) \n\
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fsw ft2, 23*4(sp) \n\
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fsw ft3, 24*4(sp) \n\
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fsw ft4, 25*4(sp) \n\
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fsw ft5, 26*4(sp) \n\
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fsw ft6, 27*4(sp) \n\
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fsw ft7, 28*4(sp) \n\
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fsw fa0, 29*4(sp) \n\
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fsw fa1, 30*4(sp) \n\
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fsw fa2, 31*4(sp) \n\
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fsw fa3, 32*4(sp) \n\
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fsw fa4, 33*4(sp) \n\
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fsw fa5, 34*4(sp) \n\
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fsw fa6, 35*4(sp) \n\
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fsw fa7, 36*4(sp) \n\
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fsw ft8, 37*4(sp) \n\
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fsw ft9, 38*4(sp) \n\
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fsw ft10, 39*4(sp) \n\
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fsw ft11, 40*4(sp) \n\
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frsr t6 \n\
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sw t6, 41*4(sp) \n");\
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}
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/*
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* Restore FPU caller registers:
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* NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 21 in the stack
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*/
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#define RESTORE_FPU_CONTEXT() { \
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__asm volatile("flw ft0, 21*4(sp) \n\
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flw ft1, 22*4(sp) \n\
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flw ft2, 23*4(sp) \n\
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flw ft3, 24*4(sp) \n\
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flw ft4, 25*4(sp) \n\
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flw ft5, 26*4(sp) \n\
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flw ft6, 27*4(sp) \n\
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flw ft7, 28*4(sp) \n\
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flw fa0, 29*4(sp) \n\
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flw fa1, 30*4(sp) \n\
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flw fa2, 31*4(sp) \n\
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flw fa3, 32*4(sp) \n\
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flw fa4, 33*4(sp) \n\
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flw fa5, 34*4(sp) \n\
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flw fa6, 35*4(sp) \n\
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flw fa7, 36*4(sp) \n\
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flw ft8, 37*4(sp) \n\
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flw ft9, 38*4(sp) \n\
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flw ft10, 39*4(sp) \n\
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flw ft11, 40*4(sp) \n\
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lw t6, 41*4(sp) \n\
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fssr t6, t6 \n");\
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}
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#else
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#define SAVE_FPU_CONTEXT()
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#define RESTORE_FPU_CONTEXT()
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#endif
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/**
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* @brief Save the caller registers based on the RISC-V ABI specification
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*/
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#define SAVE_CALLER_CONTEXT() { \
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__asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\
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__asm volatile("sw ra, 0*4(sp) \n\
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sw t0, 1*4(sp) \n\
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sw t1, 2*4(sp) \n\
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sw t2, 3*4(sp) \n\
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sw a0, 4*4(sp) \n\
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sw a1, 5*4(sp) \n\
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sw a2, 6*4(sp) \n\
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sw a3, 7*4(sp) \n\
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sw a4, 8*4(sp) \n\
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sw a5, 9*4(sp) \n\
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sw a6, 10*4(sp) \n\
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sw a7, 11*4(sp) \n\
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sw t3, 12*4(sp) \n\
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sw t4, 13*4(sp) \n\
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sw t5, 14*4(sp) \n\
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sw t6, 15*4(sp)"); \
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SAVE_FPU_CONTEXT(); \
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}
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/**
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* @brief Restore the caller registers based on the RISC-V ABI specification
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*/
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#define RESTORE_CALLER_CONTEXT() { \
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__asm volatile("lw ra, 0*4(sp) \n\
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lw t0, 1*4(sp) \n\
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lw t1, 2*4(sp) \n\
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lw t2, 3*4(sp) \n\
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lw a0, 4*4(sp) \n\
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lw a1, 5*4(sp) \n\
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lw a2, 6*4(sp) \n\
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lw a3, 7*4(sp) \n\
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lw a4, 8*4(sp) \n\
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lw a5, 9*4(sp) \n\
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lw a6, 10*4(sp) \n\
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lw a7, 11*4(sp) \n\
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lw t3, 12*4(sp) \n\
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lw t4, 13*4(sp) \n\
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lw t5, 14*4(sp) \n\
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lw t6, 15*4(sp) \n");\
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RESTORE_FPU_CONTEXT(); \
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__asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\
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}
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#ifdef __riscv_dsp
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/*
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* Save DSP context
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* NOTE: To simplify the logic, DSP context registers are always stored at word offset 20 in the stack
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*/
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#define SAVE_DSP_CONTEXT() { \
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__asm volatile("csrr t6, ucode\n\
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sw t6, 20*4(sp)\n"); \
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}
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/*
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* @brief Restore DSP context
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* @note To simplify the logic, DSP context registers are always stored at word offset 20 in the stack
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*/
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#define RESTORE_DSP_CONTEXT() {\
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__asm volatile("lw t6, 20*4(sp)\n\
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csrw ucode, t6 \n"); \
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}
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#else
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#define SAVE_DSP_CONTEXT()
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#define RESTORE_DSP_CONTEXT()
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#endif
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/*
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* @brief Enter Nested IRQ Handling
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* @note To simplify the logic, Nested IRQ related registers are stored in the stack as below:
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* MCAUSE - word offset 16 (not used in the vectored mode)
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* EPC - word offset 17
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* MSTATUS = word offset 18
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* MXSTATUS = word offset 19
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*/
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#define ENTER_NESTED_IRQ_HANDLING_M() {\
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__asm volatile("csrr t6, mepc \n\
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sw t6, 17*4(sp) \n\
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csrr t6, mstatus \n\
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sw t6, 18*4(sp) \n\
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csrr t6, %0\n\
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sw t6, 19*4(sp) \n\
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" : : "i" CSR_MSTATUS);\
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SAVE_DSP_CONTEXT(); \
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__asm volatile("li t6, %0\n" : : "i" (CSR_MSTATUS_MIE_MASK)); \
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__asm volatile("csrrs t6, mstatus, t6\n"); \
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}
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#define COMPLETE_IRQ_HANDLING_M(irq_num) {\
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__asm volatile("li t0, 0xe4000000 \n\
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li t1, 0x200004 \n\
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add t0, t0, t1 \n\
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lui t1, 0 \n\
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slli t2, t1, 0xc \n\
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add t0, t0, t2 \n");\
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__asm volatile("li t1, %0" : : "i" (irq_num) :); \
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__asm volatile("sw t1, 0(t0) \n\
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fence io, io \n\
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li t6, 1\n\
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addi t6, t6, -0x800\n\
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csrrs t6, mie, t6 \n"); \
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}
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/*
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* @brief Exit Nested IRQ Handling
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* @note To simplify the logic, Nested IRQ related registers are stored in the stack as below:
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|
* MCAUSE - word offset 16 (not used in the vectored mode)
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* EPC - word offset 17
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|
* MSTATUS = word offset 18
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|
* MXSTATUS = word offset 19
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|
*/
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|
#define EXIT_NESTED_IRQ_HANDLING_M() { \
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|
__asm volatile("csrrci t6, mstatus, 8 \n\
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|
lw t6, 18*4(sp) \n\
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|
csrw mstatus, t6 \n\
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|
lw t6, 17*4(sp) \n\
|
|
csrw mepc, t6 \n\
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|
lw t6, 19*4(sp) \n\
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|
csrw %0, t6 \n" : : "i" CSR_MSTATUS);\
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|
RESTORE_DSP_CONTEXT(); \
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|
}
|
|
|
|
|
|
/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */
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|
#define NESTED_IRQ_ENTER() \
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|
SAVE_CSR(CSR_MEPC) \
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|
SAVE_CSR(CSR_MSTATUS) \
|
|
SAVE_MXSTATUS() \
|
|
SAVE_FCSR() \
|
|
SAVE_UCODE() \
|
|
set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK);
|
|
|
|
/* @brief Nested IRQ exit macro : Restore CSRs */
|
|
#define NESTED_IRQ_EXIT() \
|
|
clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); \
|
|
RESTORE_CSR(CSR_MSTATUS) \
|
|
RESTORE_CSR(CSR_MEPC) \
|
|
RESTORE_MXSTATUS() \
|
|
RESTORE_FCSR() \
|
|
RESTORE_UCODE()
|
|
|
|
/*
|
|
* @brief Nested IRQ exit macro : Restore CSRs
|
|
* @param[in] irq Target interrupt number
|
|
*/
|
|
#define NESTED_VPLIC_COMPLETE_INTERRUPT(irq) \
|
|
do { \
|
|
clear_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \
|
|
__plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq); \
|
|
__asm volatile("fence io, io"); \
|
|
set_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \
|
|
} while(0)
|
|
|
|
#ifdef __cplusplus
|
|
#define HPM_EXTERN_C extern "C"
|
|
#else
|
|
#define HPM_EXTERN_C
|
|
#endif
|
|
|
|
#define ISR_NAME_M(irq_num) default_isr_##irq_num
|
|
/**
|
|
* @brief Declare an external interrupt handler for machine mode
|
|
*
|
|
* @param[in] irq_num - IRQ number index
|
|
* @param[in] isr - Application IRQ handler function pointer
|
|
*/
|
|
#ifndef USE_NONVECTOR_MODE
|
|
#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \
|
|
void isr(void) __attribute__((section(".isr_vector")));\
|
|
HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\
|
|
void ISR_NAME_M(irq_num)(void) {\
|
|
SAVE_CALLER_CONTEXT(); \
|
|
ENTER_NESTED_IRQ_HANDLING_M();\
|
|
__asm volatile("la t1, %0\n\t" : : "i" (isr) : );\
|
|
__asm volatile("jalr t1\n");\
|
|
EXIT_NESTED_IRQ_HANDLING_M();\
|
|
COMPLETE_IRQ_HANDLING_M(irq_num);\
|
|
RESTORE_CALLER_CONTEXT();\
|
|
__asm volatile("mret\n");\
|
|
}
|
|
#else
|
|
#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \
|
|
void isr(void) __attribute__((section(".isr_vector")));\
|
|
HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\
|
|
void ISR_NAME_M(irq_num)(void) { \
|
|
isr(); \
|
|
}
|
|
#endif
|
|
|
|
|
|
/**
|
|
* @brief Declare machine timer interrupt handler
|
|
*
|
|
* @param[in] isr - MCHTMR IRQ handler function pointer
|
|
*/
|
|
#define SDK_DECLARE_MCHTMR_ISR(isr) \
|
|
void isr(void) __attribute__((section(".isr_vector")));\
|
|
HPM_EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \
|
|
void mchtmr_isr(void) {\
|
|
isr();\
|
|
}
|
|
|
|
/**
|
|
* @brief Declare machine software interrupt handler
|
|
*
|
|
* @param[in] isr - SWI IRQ handler function pointer
|
|
*/
|
|
#define SDK_DECLARE_SWI_ISR(isr)\
|
|
void isr(void) __attribute__((section(".isr_vector")));\
|
|
HPM_EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \
|
|
void swi_isr(void) {\
|
|
isr();\
|
|
}
|
|
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* HPM_INTERRUPT_H */
|