725 lines
16 KiB
C
725 lines
16 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-03-04 stevetong459 first version
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* 2022-07-15 Aligagago add apm32F4 serie MCU support
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* 2022-12-26 luobeihai add apm32F0 serie MCU support
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*/
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#include <board.h>
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#define DBG_TAG "drv.hwtimer"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#ifdef RT_USING_HWTIMER
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static const struct rt_hwtimer_info apm32_timer_info =
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{
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.maxfreq = 1000000,
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.minfreq = 2000,
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.maxcnt = 0xFFFF,
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.cntmode = HWTIMER_CNTMODE_UP,
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};
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/* apm32 config class */
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struct apm32_timer
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{
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char *name;
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TMR_T *tmr;
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IRQn_Type irqn;
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rt_hwtimer_t device;
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};
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enum
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{
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#ifdef BSP_USING_TMR1
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TMR1_INDEX,
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#endif
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#ifdef BSP_USING_TMR2
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TMR2_INDEX,
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#endif
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#ifdef BSP_USING_TMR3
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TMR3_INDEX,
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#endif
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#ifdef BSP_USING_TMR4
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TMR4_INDEX,
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#endif
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#ifdef BSP_USING_TMR5
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TMR5_INDEX,
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#endif
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#ifdef BSP_USING_TMR6
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TMR6_INDEX,
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#endif
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#ifdef BSP_USING_TMR7
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TMR7_INDEX,
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#endif
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#ifdef BSP_USING_TMR8
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TMR8_INDEX,
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#endif
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#ifdef BSP_USING_TMR9
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TMR9_INDEX,
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#endif
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#ifdef BSP_USING_TMR10
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TMR10_INDEX,
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#endif
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#ifdef BSP_USING_TMR11
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TMR11_INDEX,
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#endif
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#ifdef BSP_USING_TMR12
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TMR12_INDEX,
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#endif
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#ifdef BSP_USING_TMR13
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TMR13_INDEX,
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#endif
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#ifdef BSP_USING_TMR14
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TMR14_INDEX,
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#endif
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#ifdef BSP_USING_TMR15
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TMR15_INDEX,
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#endif
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#ifdef BSP_USING_TMR16
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TMR16_INDEX,
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#endif
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#ifdef BSP_USING_TMR17
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TMR17_INDEX,
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#endif
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};
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static struct apm32_timer tmr_config[] =
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{
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#ifdef BSP_USING_TMR1
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{
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"timer1",
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TMR1,
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#if defined(SOC_SERIES_APM32F1)
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TMR1_UP_IRQn,
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#elif defined(SOC_SERIES_APM32F4)
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TMR1_UP_TMR10_IRQn,
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#elif defined(SOC_SERIES_APM32F0)
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TMR1_BRK_UP_TRG_COM_IRQn
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#endif
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},
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#endif
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#ifdef BSP_USING_TMR2
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{
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"timer2",
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TMR2,
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TMR2_IRQn,
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},
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#endif
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#ifdef BSP_USING_TMR3
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{
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"timer3",
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TMR3,
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TMR3_IRQn,
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},
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#endif
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#ifdef BSP_USING_TMR4
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{
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"timer4",
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TMR4,
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TMR4_IRQn,
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},
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#endif
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#ifdef BSP_USING_TMR5
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{
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"timer5",
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TMR5,
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TMR5_IRQn,
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},
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#endif
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#ifdef BSP_USING_TMR6
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{
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"timer6",
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TMR6,
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#if defined(SOC_SERIES_APM32F1) || defined(APM32F030) || defined(APM32F070)
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TMR6_IRQn,
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#elif defined(SOC_SERIES_APM32F4)
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TMR6_DAC_IRQn
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#elif defined(SOC_SERIES_APM32F0) && !defined(APM32F030) && !defined(APM32F070)
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TMR6_DAC_IRQn
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#endif
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},
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#endif
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#ifdef BSP_USING_TMR7
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{
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"timer7",
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TMR7,
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TMR7_IRQn,
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},
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#endif
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#ifdef BSP_USING_TMR8
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{
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"timer8",
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TMR8,
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#if defined(SOC_SERIES_APM32F1)
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TMR8_UP_IRQn,
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#elif defined(SOC_SERIES_APM32F4)
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TMR8_UP_TMR13_IRQn,
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#endif
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},
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#endif
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#ifdef BSP_USING_TMR9
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{
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"timer9",
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TMR9,
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TMR1_BRK_TMR9_IRQn,
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},
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#endif
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#ifdef BSP_USING_TMR10
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{
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"timer10",
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TMR10,
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TMR1_UP_TMR10_IRQn,
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},
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#endif
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#ifdef BSP_USING_TMR11
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{
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"timer11",
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TMR11,
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TMR1_TRG_COM_TMR11_IRQn,
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},
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#endif
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#ifdef BSP_USING_TMR12
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{
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"timer12",
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TMR12,
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TMR8_BRK_TMR12_IRQn,
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},
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#endif
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#ifdef BSP_USING_TMR13
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{
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"timer13",
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TMR13,
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TMR8_UP_TMR13_IRQn,
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},
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#endif
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#ifdef BSP_USING_TMR14
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{
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"timer14",
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TMR14,
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#if defined(SOC_SERIES_APM32F0)
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TMR14_IRQn,
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#elif defined(SOC_SERIES_APM32F4)
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TMR8_TRG_COM_TMR14_IRQn,
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#endif
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},
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#endif
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#ifdef BSP_USING_TMR15
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{
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"timer15",
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TMR15,
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TMR15_IRQn,
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},
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#endif
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#ifdef BSP_USING_TMR16
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{
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"timer16",
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TMR16,
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TMR16_IRQn,
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},
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#endif
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#ifdef BSP_USING_TMR17
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{
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"timer17",
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TMR17,
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TMR17_IRQn,
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},
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#endif
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};
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static rt_uint32_t apm32_hwtimer_clock_get(TMR_T *tmr)
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{
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#if defined(SOC_SERIES_APM32F0)
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uint32_t pclk1;
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pclk1 = RCM_ReadPCLKFreq();
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return (rt_uint32_t)(pclk1 * ((RCM->CFG1_B.APB1PSC != 0) ? 2 : 1));
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#else
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uint32_t pclk1, pclk2;
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RCM_ReadPCLKFreq(&pclk1, &pclk2);
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if (tmr == TMR1 || tmr == TMR8 || tmr == TMR9 || tmr == TMR10 || tmr == TMR11)
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{
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return (rt_uint32_t)(pclk2 * ((RCM->CFG_B.APB2PSC != 0) ? 2 : 1));
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}
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else
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{
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return (rt_uint32_t)(pclk1 * ((RCM->CFG_B.APB1PSC != 0) ? 2 : 1));
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}
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#endif
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}
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static void apm32_hwtimer_enable_clock(void)
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{
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#ifdef BSP_USING_TMR1
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR1);
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#endif
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#ifdef BSP_USING_TMR2
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RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR2);
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#endif
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#ifdef BSP_USING_TMR3
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RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR3);
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#endif
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#ifdef BSP_USING_TMR4
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RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR4);
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#endif
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#ifdef BSP_USING_TMR5
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RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR5);
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#endif
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#ifdef BSP_USING_TMR6
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RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR6);
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#endif
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#ifdef BSP_USING_TMR7
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RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR7);
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#endif
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#ifdef BSP_USING_TMR8
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR8);
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#endif
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#ifdef BSP_USING_TMR9
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR9);
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#endif
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#ifdef BSP_USING_TMR10
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR10);
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#endif
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#ifdef BSP_USING_TMR11
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR11);
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#endif
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#ifdef BSP_USING_TMR12
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RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR12);
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#endif
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#ifdef BSP_USING_TMR13
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RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR13);
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#endif
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#ifdef BSP_USING_TMR14
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RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_TMR14);
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#endif
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#ifdef BSP_USING_TMR15
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR15);
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#endif
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#ifdef BSP_USING_TMR16
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR16);
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#endif
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#ifdef BSP_USING_TMR17
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR17);
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#endif
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}
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static void apm32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
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{
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#if defined(SOC_SERIES_APM32F0)
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TMR_TimeBase_T base_config;
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#else
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TMR_BaseConfig_T base_config;
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#endif
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uint32_t prescaler = 0;
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struct apm32_timer *timer_config;
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RT_ASSERT(timer != RT_NULL);
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if (state)
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{
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timer_config = (struct apm32_timer *)timer->parent.user_data;
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apm32_hwtimer_enable_clock();
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prescaler = (uint32_t)(apm32_hwtimer_clock_get(timer_config->tmr) / 10000) - 1;
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base_config.period = 10000 - 1;
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#if defined(SOC_SERIES_APM32F0)
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base_config.div = prescaler;
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base_config.clockDivision = TMR_CKD_DIV1;
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if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
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{
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base_config.counterMode = TMR_COUNTER_MODE_UP;
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}
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else
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{
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base_config.counterMode = TMR_COUNTER_MODE_DOWN;
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}
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#else
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base_config.division = prescaler;
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base_config.clockDivision = TMR_CLOCK_DIV_1;
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if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
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{
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base_config.countMode = TMR_COUNTER_MODE_UP;
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}
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else
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{
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base_config.countMode = TMR_COUNTER_MODE_DOWN;
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}
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#endif
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base_config.repetitionCounter = 0;
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TMR_ConfigTimeBase(timer_config->tmr, &base_config);
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#if defined(SOC_SERIES_APM32F0)
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/* set the TIMx priority */
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NVIC_EnableIRQRequest(timer_config->irqn, 3);
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/* enable update request source */
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TMR_ConfigUPdateRequest(timer_config->tmr, TMR_UPDATE_SOURCE_REGULAR);
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#else
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/* set the TIMx priority */
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NVIC_EnableIRQRequest(timer_config->irqn, 3, 0);
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/* enable update request source */
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TMR_ConfigUpdateRequest(timer_config->tmr, TMR_UPDATE_SOURCE_REGULAR);
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#endif
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/* clear update flag */
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TMR_ClearStatusFlag(timer_config->tmr, TMR_FLAG_UPDATE);
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LOG_D("%s init success", timer_config->name);
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}
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}
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static rt_err_t apm32_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
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{
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rt_err_t result = RT_EOK;
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struct apm32_timer *timer_config = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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timer_config = (struct apm32_timer *)timer->parent.user_data;
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/* set timer_config counter */
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timer_config->tmr->CNT = 0;
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/* set timer_config autoReload */
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timer_config->tmr->AUTORLD = t - 1;
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if (opmode == HWTIMER_MODE_ONESHOT)
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{
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/* set timer to single mode */
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timer_config->tmr->CTRL1_B.SPMEN = 1;
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}
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else
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{
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timer_config->tmr->CTRL1_B.SPMEN = 0;
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}
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TMR_EnableInterrupt(timer_config->tmr, TMR_INT_UPDATE);
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#if defined(SOC_SERIES_APM32F0)
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if (timer_config->tmr == TMR1 || timer_config->tmr == TMR2 || timer_config->tmr == TMR3 || \
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timer_config->tmr == TMR15)
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#else
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if (timer_config->tmr == TMR1 || timer_config->tmr == TMR2 || timer_config->tmr == TMR3 || \
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timer_config->tmr == TMR4 || timer_config->tmr == TMR5 || timer_config->tmr == TMR8 || \
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timer_config->tmr == TMR9 || timer_config->tmr == TMR12)
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#endif
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{
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if (timer_config->tmr->SMCTRL_B.SMFSEL != 0x06)
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{
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TMR_Enable(timer_config->tmr);
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result = RT_EOK;
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}
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}
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else
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{
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TMR_Enable(timer_config->tmr);
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result = RT_EOK;
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}
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return result;
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}
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static void apm32_hwtimer_stop(rt_hwtimer_t *timer)
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{
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struct apm32_timer *timer_config = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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timer_config = (struct apm32_timer *)timer->parent.user_data;
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TMR_DisableInterrupt(timer_config->tmr, TMR_INT_UPDATE);
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TMR_Enable(timer_config->tmr);
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timer_config->tmr->CNT = 0;
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}
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static rt_err_t apm32_hwtimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
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{
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struct apm32_timer *timer_config = RT_NULL;
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rt_err_t result = RT_EOK;
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rt_uint32_t freq;
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rt_uint16_t val;
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RT_ASSERT(timer != RT_NULL);
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RT_ASSERT(arg != RT_NULL);
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timer_config = (struct apm32_timer *)timer->parent.user_data;
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switch (cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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/* set timer frequence */
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freq = *((rt_uint32_t *)arg);
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val = apm32_hwtimer_clock_get(timer_config->tmr) / freq;
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/* Configures the timer prescaler */
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timer_config->tmr->PSC_B.PSC = val - 1;
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timer_config->tmr->CEG_B.UEG = 1;
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break;
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default:
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LOG_E("invalid cmd: 0x%x\n", cmd);
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result = -RT_ENOSYS;
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break;
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}
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return result;
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}
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static rt_uint32_t apm32_hwtimer_counter_get(rt_hwtimer_t *timer)
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{
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struct apm32_timer *timer_config = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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timer_config = (struct apm32_timer *)timer->parent.user_data;
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return timer_config->tmr->CNT;
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}
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static const struct rt_hwtimer_ops apm32_hwtimer_ops =
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{
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.init = apm32_hwtimer_init,
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.start = apm32_hwtimer_start,
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.stop = apm32_hwtimer_stop,
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.count_get = apm32_hwtimer_counter_get,
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.control = apm32_hwtimer_ctrl,
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};
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#if defined(SOC_SERIES_APM32F0)
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#ifdef BSP_USING_TMR1
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void TMR1_BRK_UP_TRG_COM_IRQHandler(void)
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{
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rt_interrupt_enter();
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rt_device_hwtimer_isr(&tmr_config[TMR1_INDEX].device);
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TMR_ClearIntFlag(TMR1, TMR_INT_UPDATE);
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rt_interrupt_leave();
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}
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#endif
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#elif defined(SOC_SERIES_APM32F1)
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#ifdef BSP_USING_TMR1
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void TMR1_UP_IRQHandler(void)
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{
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rt_interrupt_enter();
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rt_device_hwtimer_isr(&tmr_config[TMR1_INDEX].device);
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TMR_ClearIntFlag(TMR1, TMR_INT_UPDATE);
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rt_interrupt_leave();
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}
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#endif
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#elif defined(SOC_SERIES_APM32F4)
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#if (defined(BSP_USING_TMR1) || defined(BSP_USING_TMR10))
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void TMR1_UP_TMR10_IRQHandler(void)
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{
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rt_interrupt_enter();
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if (TMR_ReadIntFlag(TMR1, TMR_INT_UPDATE))
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{
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rt_device_hwtimer_isr(&tmr_config[TMR1_INDEX].device);
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TMR_ClearIntFlag(TMR1, TMR_INT_UPDATE);
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}
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if (TMR_ReadIntFlag(TMR10, TMR_INT_UPDATE))
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{
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rt_device_hwtimer_isr(&tmr_config[TMR10_INDEX].device);
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TMR_ClearIntFlag(TMR10, TMR_INT_UPDATE);
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}
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rt_interrupt_leave();
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}
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#endif
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#endif
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|
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#ifdef BSP_USING_TMR2
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void TMR2_IRQHandler(void)
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|
{
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|
rt_interrupt_enter();
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rt_device_hwtimer_isr(&tmr_config[TMR2_INDEX].device);
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TMR_ClearIntFlag(TMR2, TMR_INT_UPDATE);
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rt_interrupt_leave();
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}
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#endif
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|
|
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#ifdef BSP_USING_TMR3
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void TMR3_IRQHandler(void)
|
|
{
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|
rt_interrupt_enter();
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|
rt_device_hwtimer_isr(&tmr_config[TMR3_INDEX].device);
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|
TMR_ClearIntFlag(TMR3, TMR_INT_UPDATE);
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|
rt_interrupt_leave();
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|
}
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|
#endif
|
|
|
|
#ifdef BSP_USING_TMR4
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|
void TMR4_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
rt_device_hwtimer_isr(&tmr_config[TMR4_INDEX].device);
|
|
TMR_ClearIntFlag(TMR4, TMR_INT_UPDATE);
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif
|
|
|
|
#ifdef BSP_USING_TMR5
|
|
void TMR5_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
rt_device_hwtimer_isr(&tmr_config[TMR5_INDEX].device);
|
|
TMR_ClearIntFlag(TMR5, TMR_INT_UPDATE);
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif
|
|
|
|
#ifdef BSP_USING_TMR6
|
|
#if defined(SOC_SERIES_APM32F1) || defined(APM32F030) || defined(APM32F070)
|
|
void TMR6_IRQHandler(void)
|
|
#elif defined(SOC_SERIES_APM32F4)
|
|
void TMR6_DAC_IRQHandler(void)
|
|
#elif defined(SOC_SERIES_APM32F0) && !defined(APM32F030) && !defined(APM32F070)
|
|
void TMR6_DAC_IRQHandler(void)
|
|
#endif
|
|
{
|
|
rt_interrupt_enter();
|
|
rt_device_hwtimer_isr(&tmr_config[TMR6_INDEX].device);
|
|
TMR_ClearIntFlag(TMR6, TMR_INT_UPDATE);
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif
|
|
|
|
#ifdef BSP_USING_TMR7
|
|
void TMR7_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
rt_device_hwtimer_isr(&tmr_config[TMR7_INDEX].device);
|
|
TMR_ClearIntFlag(TMR7, TMR_INT_UPDATE);
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif
|
|
|
|
#if defined(SOC_SERIES_APM32F1)
|
|
#ifdef BSP_USING_TMR8
|
|
void TMR8_UP_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
rt_device_hwtimer_isr(&tmr_config[TMR8_INDEX].device);
|
|
TMR_ClearIntFlag(TMR8, TMR_INT_UPDATE);
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif
|
|
#elif defined(SOC_SERIES_APM32F4)
|
|
#if (defined(BSP_USING_TMR8) || defined(BSP_USING_TMR13))
|
|
void TMR8_UP_TMR13_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
if (TMR_ReadIntFlag(TMR8, TMR_INT_UPDATE))
|
|
{
|
|
rt_device_hwtimer_isr(&tmr_config[TMR8_INDEX].device);
|
|
TMR_ClearIntFlag(TMR8, TMR_INT_UPDATE);
|
|
}
|
|
if (TMR_ReadIntFlag(TMR13, TMR_INT_UPDATE))
|
|
{
|
|
rt_device_hwtimer_isr(&tmr_config[TMR13_INDEX].device);
|
|
TMR_ClearIntFlag(TMR13, TMR_INT_UPDATE);
|
|
}
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef BSP_USING_TMR9
|
|
void TMR1_BRK_TMR9_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
rt_device_hwtimer_isr(&tmr_config[TMR9_INDEX].device);
|
|
TMR_ClearIntFlag(TMR9, TMR_INT_UPDATE);
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif
|
|
|
|
#ifdef BSP_USING_TMR11
|
|
void TMR1_TRG_COM_TMR11_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
rt_device_hwtimer_isr(&tmr_config[TMR11_INDEX].device);
|
|
TMR_ClearIntFlag(TMR11, TMR_INT_UPDATE);
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif
|
|
|
|
#ifdef BSP_USING_TMR12
|
|
void TMR8_BRK_TMR12_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
rt_device_hwtimer_isr(&tmr_config[TMR12_INDEX].device);
|
|
TMR_ClearIntFlag(TMR12, TMR_INT_UPDATE);
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif
|
|
|
|
#ifdef BSP_USING_TMR14
|
|
#if defined(SOC_SERIES_APM32F0)
|
|
void TMR14_IRQHandler(void)
|
|
#elif defined(SOC_SERIES_APM32F4)
|
|
void TMR8_TRG_COM_TMR14_IRQHandler(void)
|
|
#endif
|
|
{
|
|
rt_interrupt_enter();
|
|
rt_device_hwtimer_isr(&tmr_config[TMR14_INDEX].device);
|
|
TMR_ClearIntFlag(TMR14, TMR_INT_UPDATE);
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif
|
|
|
|
#ifdef BSP_USING_TMR15
|
|
void TMR15_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
rt_device_hwtimer_isr(&tmr_config[TMR15_INDEX].device);
|
|
TMR_ClearIntFlag(TMR15, TMR_INT_UPDATE);
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif
|
|
|
|
#ifdef BSP_USING_TMR16
|
|
void TMR16_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
rt_device_hwtimer_isr(&tmr_config[TMR16_INDEX].device);
|
|
TMR_ClearIntFlag(TMR16, TMR_INT_UPDATE);
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif
|
|
|
|
#ifdef BSP_USING_TMR17
|
|
void TMR17_IRQHandler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
rt_device_hwtimer_isr(&tmr_config[TMR17_INDEX].device);
|
|
TMR_ClearIntFlag(TMR17, TMR_INT_UPDATE);
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif
|
|
|
|
static int rt_hw_hwtimer_init(void)
|
|
{
|
|
int i = 0;
|
|
int result = RT_EOK;
|
|
|
|
for (i = 0; i < sizeof(tmr_config) / sizeof(tmr_config[0]); i++)
|
|
{
|
|
tmr_config[i].device.info = &apm32_timer_info;
|
|
tmr_config[i].device.ops = &apm32_hwtimer_ops;
|
|
if (rt_device_hwtimer_register(&tmr_config[i].device, tmr_config[i].name, &tmr_config[i]) == RT_EOK)
|
|
{
|
|
LOG_D("%s register success", tmr_config[i].name);
|
|
}
|
|
else
|
|
{
|
|
LOG_E("%s register failed", tmr_config[i].name);
|
|
result = -RT_ERROR;
|
|
}
|
|
}
|
|
|
|
return result;
|
|
}
|
|
INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
|
|
|
|
#endif /* RT_USING_HWTIMER */
|