694 lines
25 KiB
C
694 lines
25 KiB
C
/*
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* The Clear BSD License
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_pwm.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.pwm"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get the instance from the base address
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*
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* @param base PWM peripheral base address
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*
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* @return The PWM module instance
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*/
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static uint32_t PWM_GetInstance(PWM_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to PWM bases for each instance. */
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static PWM_Type *const s_pwmBases[] = PWM_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to PWM clocks for each PWM submodule. */
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static const clock_ip_name_t s_pwmClocks[][FSL_FEATURE_PWM_SUBMODULE_COUNT] = PWM_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t PWM_GetInstance(PWM_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_pwmBases); instance++)
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{
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if (s_pwmBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_pwmBases));
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return instance;
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}
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status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config)
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{
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assert(config);
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uint16_t reg;
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/* Source clock for submodule 0 cannot be itself */
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if ((config->clockSource == kPWM_Submodule0Clock) && (subModule == kPWM_Module_0))
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{
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return kStatus_Fail;
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}
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/* Reload source select clock for submodule 0 cannot be master reload */
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if ((config->reloadSelect == kPWM_MasterReload) && (subModule == kPWM_Module_0))
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{
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return kStatus_Fail;
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}
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate the PWM submodule clock*/
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CLOCK_EnableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Clear the fault status flags */
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base->FSTS |= PWM_FSTS_FFLAG_MASK;
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reg = base->SM[subModule].CTRL2;
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/* Setup the submodule clock-source, control source of the INIT signal,
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* source of the force output signal, operation in debug & wait modes and reload source select
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*/
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reg &= ~(PWM_CTRL2_CLK_SEL_MASK | PWM_CTRL2_FORCE_SEL_MASK | PWM_CTRL2_INIT_SEL_MASK | PWM_CTRL2_INDEP_MASK |
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PWM_CTRL2_WAITEN_MASK | PWM_CTRL2_DBGEN_MASK | PWM_CTRL2_RELOAD_SEL_MASK);
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reg |= (PWM_CTRL2_CLK_SEL(config->clockSource) | PWM_CTRL2_FORCE_SEL(config->forceTrigger) |
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PWM_CTRL2_INIT_SEL(config->initializationControl) | PWM_CTRL2_DBGEN(config->enableDebugMode) |
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PWM_CTRL2_WAITEN(config->enableWait) | PWM_CTRL2_RELOAD_SEL(config->reloadSelect));
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/* Setup PWM A & B to be independent or a complementary-pair */
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switch (config->pairOperation)
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{
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case kPWM_Independent:
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reg |= PWM_CTRL2_INDEP_MASK;
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break;
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case kPWM_ComplementaryPwmA:
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base->MCTRL &= ~(1U << (PWM_MCTRL_IPOL_SHIFT + subModule));
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break;
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case kPWM_ComplementaryPwmB:
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base->MCTRL |= (1U << (PWM_MCTRL_IPOL_SHIFT + subModule));
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break;
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default:
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break;
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}
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base->SM[subModule].CTRL2 = reg;
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reg = base->SM[subModule].CTRL;
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/* Setup the clock prescale, load mode and frequency */
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reg &= ~(PWM_CTRL_PRSC_MASK | PWM_CTRL_LDFQ_MASK | PWM_CTRL_LDMOD_MASK);
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reg |= (PWM_CTRL_PRSC(config->prescale) | PWM_CTRL_LDFQ(config->reloadFrequency));
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/* Setup register reload logic */
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switch (config->reloadLogic)
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{
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case kPWM_ReloadImmediate:
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reg |= PWM_CTRL_LDMOD_MASK;
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break;
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case kPWM_ReloadPwmHalfCycle:
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reg |= PWM_CTRL_HALF_MASK;
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reg &= ~PWM_CTRL_FULL_MASK;
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break;
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case kPWM_ReloadPwmFullCycle:
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reg &= ~PWM_CTRL_HALF_MASK;
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reg |= PWM_CTRL_FULL_MASK;
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break;
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case kPWM_ReloadPwmHalfAndFullCycle:
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reg |= PWM_CTRL_HALF_MASK;
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reg |= PWM_CTRL_FULL_MASK;
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break;
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default:
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break;
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}
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base->SM[subModule].CTRL = reg;
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/* Setup the fault filter */
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if (base->FFILT & PWM_FFILT_FILT_PER_MASK)
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{
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/* When changing values for fault period from a non-zero value, first write a value of 0
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* to clear the filter
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*/
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base->FFILT &= ~(PWM_FFILT_FILT_PER_MASK);
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}
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base->FFILT = (PWM_FFILT_FILT_CNT(config->faultFilterCount) | PWM_FFILT_FILT_PER(config->faultFilterPeriod));
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/* Issue a Force trigger event when configured to trigger locally */
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if (config->forceTrigger == kPWM_Force_Local)
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{
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base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE(1U);
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}
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return kStatus_Success;
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}
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void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule)
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{
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/* Stop the submodule */
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base->MCTRL &= ~(1U << (PWM_MCTRL_RUN_SHIFT + subModule));
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Gate the PWM submodule clock*/
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CLOCK_DisableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void PWM_GetDefaultConfig(pwm_config_t *config)
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{
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assert(config);
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/* PWM is paused in debug mode */
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config->enableDebugMode = false;
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/* PWM is paused in wait mode */
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config->enableWait = false;
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/* PWM module uses the local reload signal to reload registers */
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config->reloadSelect = kPWM_LocalReload;
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/* Fault filter count is set to 0 */
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config->faultFilterCount = 0;
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/* Fault filter period is set to 0 which disables the fault filter */
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config->faultFilterPeriod = 0;
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/* Use the IP Bus clock as source clock for the PWM submodule */
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config->clockSource = kPWM_BusClock;
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/* Clock source prescale is set to divide by 1*/
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config->prescale = kPWM_Prescale_Divide_1;
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/* Local sync causes initialization */
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config->initializationControl = kPWM_Initialize_LocalSync;
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/* The local force signal, CTRL2[FORCE], from the submodule is used to force updates */
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config->forceTrigger = kPWM_Force_Local;
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/* PWM reload frequency, reload opportunity is PWM half cycle or full cycle.
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* This field is not used in Immediate reload mode
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*/
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config->reloadFrequency = kPWM_LoadEveryOportunity;
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/* Buffered-registers get loaded with new values as soon as LDOK bit is set */
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config->reloadLogic = kPWM_ReloadImmediate;
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/* PWM A & PWM B operate as 2 independent channels */
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config->pairOperation = kPWM_Independent;
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}
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status_t PWM_SetupPwm(PWM_Type *base,
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pwm_submodule_t subModule,
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const pwm_signal_param_t *chnlParams,
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uint8_t numOfChnls,
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pwm_mode_t mode,
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uint32_t pwmFreq_Hz,
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uint32_t srcClock_Hz)
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{
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assert(chnlParams);
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assert(pwmFreq_Hz);
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assert(numOfChnls);
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assert(srcClock_Hz);
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uint32_t pwmClock;
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uint16_t pulseCnt = 0, pwmHighPulse = 0;
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int16_t modulo = 0;
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uint8_t i, polarityShift = 0, outputEnableShift = 0;
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if (numOfChnls > 2)
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{
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/* Each submodule has 2 signals; PWM A & PWM B */
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return kStatus_Fail;
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}
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/* Divide the clock by the prescale value */
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pwmClock = (srcClock_Hz / (1U << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT)));
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pulseCnt = (pwmClock / pwmFreq_Hz);
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/* Setup each PWM channel */
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for (i = 0; i < numOfChnls; i++)
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{
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/* Calculate pulse width */
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pwmHighPulse = (pulseCnt * chnlParams->dutyCyclePercent) / 100;
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/* Setup the different match registers to generate the PWM signal */
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switch (mode)
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{
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case kPWM_SignedCenterAligned:
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/* Setup the PWM period for a signed center aligned signal */
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modulo = pulseCnt >> 1;
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/* Indicates the start of the PWM period */
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base->SM[subModule].INIT = (-modulo);
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/* Indicates the center value */
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base->SM[subModule].VAL0 = 0;
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/* Indicates the end of the PWM period */
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base->SM[subModule].VAL1 = modulo;
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/* Setup the PWM dutycycle */
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if (chnlParams->pwmChannel == kPWM_PwmA)
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{
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base->SM[subModule].VAL2 = (-(pwmHighPulse / 2));
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base->SM[subModule].VAL3 = (pwmHighPulse / 2);
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}
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else
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{
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base->SM[subModule].VAL4 = (-(pwmHighPulse / 2));
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base->SM[subModule].VAL5 = (pwmHighPulse / 2);
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}
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break;
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case kPWM_CenterAligned:
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/* Setup the PWM period for an unsigned center aligned signal */
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/* Indicates the start of the PWM period */
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base->SM[subModule].INIT = 0;
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/* Indicates the center value */
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base->SM[subModule].VAL0 = (pulseCnt / 2);
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/* Indicates the end of the PWM period */
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base->SM[subModule].VAL1 = pulseCnt;
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/* Setup the PWM dutycycle */
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if (chnlParams->pwmChannel == kPWM_PwmA)
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{
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base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2);
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base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2);
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}
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else
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{
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base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2);
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base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2);
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}
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break;
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case kPWM_SignedEdgeAligned:
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/* Setup the PWM period for a signed edge aligned signal */
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modulo = pulseCnt >> 1;
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/* Indicates the start of the PWM period */
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base->SM[subModule].INIT = (-modulo);
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/* Indicates the center value */
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base->SM[subModule].VAL0 = 0;
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/* Indicates the end of the PWM period */
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base->SM[subModule].VAL1 = modulo;
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/* Setup the PWM dutycycle */
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if (chnlParams->pwmChannel == kPWM_PwmA)
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{
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base->SM[subModule].VAL2 = (-modulo);
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base->SM[subModule].VAL3 = (-modulo + pwmHighPulse);
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}
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else
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{
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base->SM[subModule].VAL4 = (-modulo);
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base->SM[subModule].VAL5 = (-modulo + pwmHighPulse);
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}
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break;
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case kPWM_EdgeAligned:
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/* Setup the PWM period for a unsigned edge aligned signal */
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/* Indicates the start of the PWM period */
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base->SM[subModule].INIT = 0;
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/* Indicates the center value */
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base->SM[subModule].VAL0 = (pulseCnt / 2);
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/* Indicates the end of the PWM period */
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base->SM[subModule].VAL1 = pulseCnt;
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/* Setup the PWM dutycycle */
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if (chnlParams->pwmChannel == kPWM_PwmA)
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{
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base->SM[subModule].VAL2 = 0;
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base->SM[subModule].VAL3 = pwmHighPulse;
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}
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else
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{
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base->SM[subModule].VAL4 = 0;
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base->SM[subModule].VAL5 = pwmHighPulse;
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}
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break;
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default:
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break;
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}
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/* Setup register shift values based on the channel being configured.
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* Also setup the deadtime value
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*/
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if (chnlParams->pwmChannel == kPWM_PwmA)
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{
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polarityShift = PWM_OCTRL_POLA_SHIFT;
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outputEnableShift = PWM_OUTEN_PWMA_EN_SHIFT;
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base->SM[subModule].DTCNT0 = PWM_DTCNT0_DTCNT0(chnlParams->deadtimeValue);
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}
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else
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{
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polarityShift = PWM_OCTRL_POLB_SHIFT;
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outputEnableShift = PWM_OUTEN_PWMB_EN_SHIFT;
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base->SM[subModule].DTCNT1 = PWM_DTCNT1_DTCNT1(chnlParams->deadtimeValue);
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}
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/* Setup signal active level */
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if (chnlParams->level == kPWM_HighTrue)
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{
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base->SM[subModule].OCTRL &= ~(1U << polarityShift);
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}
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else
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{
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base->SM[subModule].OCTRL |= (1U << polarityShift);
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}
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/* Enable PWM output */
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base->OUTEN |= (1U << (outputEnableShift + subModule));
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/* Get the next channel parameters */
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chnlParams++;
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}
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return kStatus_Success;
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}
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void PWM_UpdatePwmDutycycle(PWM_Type *base,
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pwm_submodule_t subModule,
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pwm_channels_t pwmSignal,
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pwm_mode_t currPwmMode,
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uint8_t dutyCyclePercent)
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{
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assert(dutyCyclePercent <= 100);
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assert(pwmSignal < 2);
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uint16_t pulseCnt = 0, pwmHighPulse = 0;
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int16_t modulo = 0;
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switch (currPwmMode)
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{
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case kPWM_SignedCenterAligned:
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modulo = base->SM[subModule].VAL1;
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pulseCnt = modulo * 2;
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/* Calculate pulse width */
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pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100;
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/* Setup the PWM dutycycle */
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if (pwmSignal == kPWM_PwmA)
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{
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base->SM[subModule].VAL2 = (-(pwmHighPulse / 2));
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base->SM[subModule].VAL3 = (pwmHighPulse / 2);
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}
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else
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{
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base->SM[subModule].VAL4 = (-(pwmHighPulse / 2));
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base->SM[subModule].VAL5 = (pwmHighPulse / 2);
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}
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break;
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case kPWM_CenterAligned:
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pulseCnt = base->SM[subModule].VAL1;
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/* Calculate pulse width */
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pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100;
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/* Setup the PWM dutycycle */
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if (pwmSignal == kPWM_PwmA)
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{
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base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2);
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base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2);
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}
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else
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{
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base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2);
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base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2);
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}
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break;
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case kPWM_SignedEdgeAligned:
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modulo = base->SM[subModule].VAL1;
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pulseCnt = modulo * 2;
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/* Calculate pulse width */
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pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100;
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/* Setup the PWM dutycycle */
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if (pwmSignal == kPWM_PwmA)
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{
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base->SM[subModule].VAL2 = (-modulo);
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base->SM[subModule].VAL3 = (-modulo + pwmHighPulse);
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}
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else
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{
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base->SM[subModule].VAL4 = (-modulo);
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base->SM[subModule].VAL5 = (-modulo + pwmHighPulse);
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}
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break;
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case kPWM_EdgeAligned:
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pulseCnt = base->SM[subModule].VAL1;
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/* Calculate pulse width */
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pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100;
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/* Setup the PWM dutycycle */
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if (pwmSignal == kPWM_PwmA)
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{
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base->SM[subModule].VAL2 = 0;
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base->SM[subModule].VAL3 = pwmHighPulse;
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}
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else
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{
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base->SM[subModule].VAL4 = 0;
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base->SM[subModule].VAL5 = pwmHighPulse;
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}
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break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
void PWM_SetupInputCapture(PWM_Type *base,
|
|
pwm_submodule_t subModule,
|
|
pwm_channels_t pwmChannel,
|
|
const pwm_input_capture_param_t *inputCaptureParams)
|
|
{
|
|
uint32_t reg = 0;
|
|
switch (pwmChannel)
|
|
{
|
|
case kPWM_PwmA:
|
|
/* Setup the capture paramters for PWM A pin */
|
|
reg = (PWM_CAPTCTRLA_INP_SELA(inputCaptureParams->captureInputSel) |
|
|
PWM_CAPTCTRLA_EDGA0(inputCaptureParams->edge0) | PWM_CAPTCTRLA_EDGA1(inputCaptureParams->edge1) |
|
|
PWM_CAPTCTRLA_ONESHOTA(inputCaptureParams->enableOneShotCapture) |
|
|
PWM_CAPTCTRLA_CFAWM(inputCaptureParams->fifoWatermark));
|
|
/* Enable the edge counter if using the output edge counter */
|
|
if (inputCaptureParams->captureInputSel)
|
|
{
|
|
reg |= PWM_CAPTCTRLA_EDGCNTA_EN_MASK;
|
|
}
|
|
/* Enable input capture operation */
|
|
reg |= PWM_CAPTCTRLA_ARMA_MASK;
|
|
|
|
base->SM[subModule].CAPTCTRLA = reg;
|
|
|
|
/* Setup the compare value when using the edge counter as source */
|
|
base->SM[subModule].CAPTCOMPA = PWM_CAPTCOMPA_EDGCMPA(inputCaptureParams->edgeCompareValue);
|
|
/* Setup PWM A pin for input capture */
|
|
base->OUTEN &= ~(1U << (PWM_OUTEN_PWMA_EN_SHIFT + subModule));
|
|
|
|
break;
|
|
case kPWM_PwmB:
|
|
/* Setup the capture paramters for PWM B pin */
|
|
reg = (PWM_CAPTCTRLB_INP_SELB(inputCaptureParams->captureInputSel) |
|
|
PWM_CAPTCTRLB_EDGB0(inputCaptureParams->edge0) | PWM_CAPTCTRLB_EDGB1(inputCaptureParams->edge1) |
|
|
PWM_CAPTCTRLB_ONESHOTB(inputCaptureParams->enableOneShotCapture) |
|
|
PWM_CAPTCTRLB_CFBWM(inputCaptureParams->fifoWatermark));
|
|
/* Enable the edge counter if using the output edge counter */
|
|
if (inputCaptureParams->captureInputSel)
|
|
{
|
|
reg |= PWM_CAPTCTRLB_EDGCNTB_EN_MASK;
|
|
}
|
|
/* Enable input capture operation */
|
|
reg |= PWM_CAPTCTRLB_ARMB_MASK;
|
|
|
|
base->SM[subModule].CAPTCTRLB = reg;
|
|
|
|
/* Setup the compare value when using the edge counter as source */
|
|
base->SM[subModule].CAPTCOMPB = PWM_CAPTCOMPB_EDGCMPB(inputCaptureParams->edgeCompareValue);
|
|
/* Setup PWM B pin for input capture */
|
|
base->OUTEN &= ~(1U << (PWM_OUTEN_PWMB_EN_SHIFT + subModule));
|
|
break;
|
|
case kPWM_PwmX:
|
|
reg = (PWM_CAPTCTRLX_INP_SELX(inputCaptureParams->captureInputSel) |
|
|
PWM_CAPTCTRLX_EDGX0(inputCaptureParams->edge0) | PWM_CAPTCTRLX_EDGX1(inputCaptureParams->edge1) |
|
|
PWM_CAPTCTRLX_ONESHOTX(inputCaptureParams->enableOneShotCapture) |
|
|
PWM_CAPTCTRLX_CFXWM(inputCaptureParams->fifoWatermark));
|
|
/* Enable the edge counter if using the output edge counter */
|
|
if (inputCaptureParams->captureInputSel)
|
|
{
|
|
reg |= PWM_CAPTCTRLX_EDGCNTX_EN_MASK;
|
|
}
|
|
/* Enable input capture operation */
|
|
reg |= PWM_CAPTCTRLX_ARMX_MASK;
|
|
|
|
base->SM[subModule].CAPTCTRLX = reg;
|
|
|
|
/* Setup the compare value when using the edge counter as source */
|
|
base->SM[subModule].CAPTCOMPX = PWM_CAPTCOMPX_EDGCMPX(inputCaptureParams->edgeCompareValue);
|
|
/* Setup PWM X pin for input capture */
|
|
base->OUTEN &= ~(1U << (PWM_OUTEN_PWMX_EN_SHIFT + subModule));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams)
|
|
{
|
|
assert(faultParams);
|
|
uint16_t reg;
|
|
|
|
reg = base->FCTRL;
|
|
/* Set the faults level-settting */
|
|
if (faultParams->faultLevel)
|
|
{
|
|
reg |= (1U << (PWM_FCTRL_FLVL_SHIFT + faultNum));
|
|
}
|
|
else
|
|
{
|
|
reg &= ~(1U << (PWM_FCTRL_FLVL_SHIFT + faultNum));
|
|
}
|
|
/* Set the fault clearing mode */
|
|
if (faultParams->faultClearingMode)
|
|
{
|
|
/* Use manual fault clearing */
|
|
reg &= ~(1U << (PWM_FCTRL_FAUTO_SHIFT + faultNum));
|
|
if (faultParams->faultClearingMode == kPWM_ManualSafety)
|
|
{
|
|
/* Use manual fault clearing with safety mode enabled */
|
|
reg |= (1U << (PWM_FCTRL_FSAFE_SHIFT + faultNum));
|
|
}
|
|
else
|
|
{
|
|
/* Use manual fault clearing with safety mode disabled */
|
|
reg &= ~(1U << (PWM_FCTRL_FSAFE_SHIFT + faultNum));
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Use automatic fault clearing */
|
|
reg |= (1U << (PWM_FCTRL_FAUTO_SHIFT + faultNum));
|
|
}
|
|
base->FCTRL = reg;
|
|
|
|
/* Set the combinational path option */
|
|
if (faultParams->enableCombinationalPath)
|
|
{
|
|
/* Combinational path from the fault input to the PWM output is available */
|
|
base->FCTRL2 &= ~(1U << faultNum);
|
|
}
|
|
else
|
|
{
|
|
/* No combinational path available, only fault filter & latch signal can disable PWM output */
|
|
base->FCTRL2 |= (1U << faultNum);
|
|
}
|
|
|
|
/* Initially clear both recovery modes */
|
|
reg = base->FSTS;
|
|
reg &= ~((1U << (PWM_FSTS_FFULL_SHIFT + faultNum)) | (1U << (PWM_FSTS_FHALF_SHIFT + faultNum)));
|
|
/* Setup fault recovery */
|
|
switch (faultParams->recoverMode)
|
|
{
|
|
case kPWM_NoRecovery:
|
|
break;
|
|
case kPWM_RecoverHalfCycle:
|
|
reg |= (1U << (PWM_FSTS_FHALF_SHIFT + faultNum));
|
|
break;
|
|
case kPWM_RecoverFullCycle:
|
|
reg |= (1U << (PWM_FSTS_FFULL_SHIFT + faultNum));
|
|
break;
|
|
case kPWM_RecoverHalfAndFullCycle:
|
|
reg |= (1U << (PWM_FSTS_FHALF_SHIFT + faultNum));
|
|
reg |= (1U << (PWM_FSTS_FFULL_SHIFT + faultNum));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
base->FSTS = reg;
|
|
}
|
|
|
|
void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode)
|
|
|
|
{
|
|
uint16_t shift;
|
|
uint16_t reg;
|
|
|
|
/* DTSRCSEL register has 4 bits per submodule; 2 bits for PWM A and 2 bits for PWM B */
|
|
shift = subModule * 4 + pwmChannel * 2;
|
|
|
|
/* Setup the signal to be passed upon occurrence of a FORCE_OUT signal */
|
|
reg = base->DTSRCSEL;
|
|
reg &= ~(0x3U << shift);
|
|
reg |= (uint16_t)((uint16_t)mode << shift);
|
|
base->DTSRCSEL = reg;
|
|
}
|
|
|
|
void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)
|
|
{
|
|
/* Upper 16 bits are for related to the submodule */
|
|
base->SM[subModule].INTEN |= (mask & 0xFFFFU);
|
|
/* Fault related interrupts */
|
|
base->FCTRL |= ((mask >> 16U) & PWM_FCTRL_FIE_MASK);
|
|
}
|
|
|
|
void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)
|
|
{
|
|
base->SM[subModule].INTEN &= ~(mask & 0xFFFF);
|
|
base->FCTRL &= ~((mask >> 16U) & PWM_FCTRL_FIE_MASK);
|
|
}
|
|
|
|
uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule)
|
|
{
|
|
uint32_t enabledInterrupts;
|
|
|
|
enabledInterrupts = base->SM[subModule].INTEN;
|
|
enabledInterrupts |= ((uint32_t)(base->FCTRL & PWM_FCTRL_FIE_MASK) << 16U);
|
|
return enabledInterrupts;
|
|
}
|
|
|
|
uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule)
|
|
{
|
|
uint32_t statusFlags;
|
|
|
|
statusFlags = base->SM[subModule].STS;
|
|
statusFlags |= ((uint32_t)(base->FSTS & PWM_FSTS_FFLAG_MASK) << 16U);
|
|
|
|
return statusFlags;
|
|
}
|
|
|
|
void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)
|
|
{
|
|
uint16_t reg;
|
|
|
|
base->SM[subModule].STS = (mask & 0xFFFFU);
|
|
reg = base->FSTS;
|
|
/* Clear the fault flags and set only the ones we wish to clear as the fault flags are cleared
|
|
* by writing a login one
|
|
*/
|
|
reg &= ~(PWM_FSTS_FFLAG_MASK);
|
|
reg |= ((mask >> 16U) & PWM_FSTS_FFLAG_MASK);
|
|
base->FSTS = reg;
|
|
}
|