637 lines
22 KiB
C
637 lines
22 KiB
C
/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_dma.h"
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#include "fsl_i2s_dma.h"
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#include "fsl_flexcomm.h"
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#include <string.h>
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s_dma"
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#endif
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#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t))
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#define DMA_DESCRIPTORS (2U)
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/*<! @brief Structure for statically allocated private data. */
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typedef struct _i2s_dma_private_handle
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{
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I2S_Type *base; /*!< I2S base address */
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i2s_dma_handle_t *handle; /*!< I2S handle */
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volatile uint16_t enqueuedBytes[DMA_DESCRIPTORS]; /*!< Number of bytes being transferred by DMA descriptors */
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volatile uint8_t enqueuedBytesStart; /*!< First item in enqueuedBytes (for reading) */
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volatile uint8_t enqueuedBytesEnd; /*!< Last item in enqueuedBytes (for adding) */
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volatile uint8_t
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dmaDescriptorsUsed; /*!< Number of DMA descriptors with valid data (in queue, excluding initial descriptor) */
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volatile uint8_t
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descriptor; /*!< Index of next DMA descriptor in s_DmaDescriptors to be configured with data (does not include
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I2S instance offset) */
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volatile uint8_t queueDescriptor; /*!< Queue index of buffer to be actually consumed by DMA
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* (queueUser - advanced when user adds a buffer,
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* queueDescriptor - advanced when user buffer queued to DMA,
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* queueDriver - advanced when DMA queued buffer sent out to I2S) */
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volatile i2s_transfer_t descriptorQueue[I2S_NUM_BUFFERS]; /*!< Transfer data to be queued to DMA */
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volatile bool intA; /*!< If next scheduled DMA transfer will cause interrupt A or B */
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} i2s_dma_private_handle_t;
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/*! @brief I2S DMA transfer private state. */
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enum _i2s_dma_state
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{
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kI2S_DmaStateIdle = 0x0U, /*!< I2S is in idle state */
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kI2S_DmaStateTx, /*!< I2S is busy transmitting data */
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kI2S_DmaStateRx, /*!< I2S is busy receiving data */
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};
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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static status_t I2S_EnqueueUserBuffer(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
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static uint32_t I2S_GetInstance(I2S_Type *base);
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static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle);
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static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle);
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static void I2S_TxEnableDMA(I2S_Type *base, bool enable);
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static void I2S_RxEnableDMA(I2S_Type *base, bool enable);
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static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer);
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static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle);
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static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*<! @brief DMA transfer descriptors. */
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#if defined(__ICCARM__)
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#pragma data_alignment = 16
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static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
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#elif defined(__CC_ARM)
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__attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
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#elif defined(__GNUC__)
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__attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
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#endif
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/*<! @brief Buffer with dummy TX data. */
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#if defined(__ICCARM__)
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#pragma data_alignment = 4
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static uint32_t s_DummyBufferTx = 0U;
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#elif defined(__CC_ARM)
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__attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U;
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#elif defined(__GNUC__)
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__attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U;
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#endif
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/*<! @brief Buffer to fill with RX data to discard. */
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#if defined(__ICCARM__)
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#pragma data_alignment = 4
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static uint32_t s_DummyBufferRx = 0U;
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#elif defined(__CC_ARM)
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__attribute__((aligned(4))) static uint32_t s_DummyBufferRx = 0U;
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#elif defined(__GNUC__)
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__attribute__((aligned(4))) static uint32_t s_DummyBufferRx = 0U;
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#endif
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/*<! @brief Private array of data associated with available I2S peripherals. */
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static i2s_dma_private_handle_t s_DmaPrivateHandle[FSL_FEATURE_SOC_I2S_COUNT];
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/*<! @brief Base addresses of available I2S peripherals. */
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static const uint32_t s_I2sBaseAddrs[FSL_FEATURE_SOC_I2S_COUNT] = I2S_BASE_ADDRS;
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/*******************************************************************************
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* Code
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******************************************************************************/
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static status_t I2S_EnqueueUserBuffer(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
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{
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uint32_t instance = I2S_GetInstance(base);
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i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
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/* Validate input data and tranfer buffer */
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assert(handle);
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if (!handle)
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{
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return kStatus_InvalidArgument;
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}
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assert((((uint32_t)transfer.data) % 4U) == 0U);
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if ((((uint32_t)transfer.data) % 4U) != 0U)
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{
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/* Data not 4-bytes aligned */
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return kStatus_InvalidArgument;
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}
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assert(transfer.dataSize != 0U);
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if (transfer.dataSize == 0U)
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{
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/* No data to send or receive */
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return kStatus_InvalidArgument;
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}
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assert((transfer.dataSize % 4U) == 0U);
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if ((transfer.dataSize % 4U) != 0U)
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{
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/* Data length not multiply of 4 bytes */
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return kStatus_InvalidArgument;
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}
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if (handle->i2sQueue[handle->queueUser].dataSize)
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{
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/* Previously prepared buffers not processed yet, reject request */
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return kStatus_I2S_Busy;
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}
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/* Enqueue data */
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privateHandle->descriptorQueue[handle->queueUser].data = transfer.data;
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privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize;
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handle->i2sQueue[handle->queueUser].data = transfer.data;
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handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize;
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handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS;
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return kStatus_Success;
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}
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static uint32_t I2S_GetInstance(I2S_Type *base)
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{
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uint32_t i;
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for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++)
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{
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if ((uint32_t)base == s_I2sBaseAddrs[i])
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{
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return i;
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}
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}
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assert(false);
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return 0U;
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}
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static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle)
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{
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DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel);
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}
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static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle)
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{
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if (handle->state != kI2S_DmaStateIdle)
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{
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DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel);
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}
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}
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void I2S_TxTransferCreateHandleDMA(I2S_Type *base,
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i2s_dma_handle_t *handle,
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dma_handle_t *dmaHandle,
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i2s_dma_transfer_callback_t callback,
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void *userData)
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{
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assert(handle);
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assert(dmaHandle);
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uint32_t instance = I2S_GetInstance(base);
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i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
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memset(handle, 0U, sizeof(*handle));
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handle->state = kI2S_DmaStateIdle;
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handle->dmaHandle = dmaHandle;
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handle->completionCallback = callback;
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handle->userData = userData;
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memset(privateHandle, 0U, sizeof(*privateHandle));
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privateHandle->base = base;
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privateHandle->handle = handle;
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DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle);
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}
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status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
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{
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status_t status;
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I2S_DisableDMAInterrupts(handle);
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/* Enqueue transfer buffer */
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status = I2S_EnqueueUserBuffer(base, handle, transfer);
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if (status != kStatus_Success)
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{
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I2S_EnableDMAInterrupts(handle);
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return status;
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}
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/* Initialize DMA transfer */
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if (handle->state == kI2S_DmaStateIdle)
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{
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handle->state = kI2S_DmaStateTx;
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status = I2S_StartTransferDMA(base, handle);
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if (status != kStatus_Success)
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{
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I2S_EnableDMAInterrupts(handle);
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return status;
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}
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}
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I2S_AddTransferDMA(base, handle);
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I2S_EnableDMAInterrupts(handle);
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return kStatus_Success;
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}
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void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle)
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{
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assert(handle);
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assert(handle->dmaHandle);
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uint32_t instance = I2S_GetInstance(base);
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i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
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I2S_DisableDMAInterrupts(handle);
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/* Abort operation */
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DMA_AbortTransfer(handle->dmaHandle);
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if (handle->state == kI2S_DmaStateTx)
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{
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/* Wait until all transmitted data get out of FIFO */
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while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U)
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{
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}
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/* The last piece of valid data can be still being transmitted from I2S at this moment */
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/* Write additional data to FIFO */
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base->FIFOWR = 0U;
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while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U)
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{
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}
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/* At this moment the additional data are out of FIFO, starting being transmitted.
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* This means the preceding valid data has been just transmitted and we can stop I2S. */
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I2S_TxEnableDMA(base, false);
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}
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else
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{
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I2S_RxEnableDMA(base, false);
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}
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I2S_Disable(base);
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/* Reset state */
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handle->state = kI2S_DmaStateIdle;
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/* Clear transfer queue */
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memset((void *)&(handle->i2sQueue), 0U, sizeof(handle->i2sQueue));
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handle->queueDriver = 0U;
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handle->queueUser = 0U;
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/* Clear internal state */
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memset((void *)&(privateHandle->descriptorQueue), 0U, sizeof(privateHandle->descriptorQueue));
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memset((void *)&(privateHandle->enqueuedBytes), 0U, sizeof(privateHandle->enqueuedBytes));
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privateHandle->enqueuedBytesStart = 0U;
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privateHandle->enqueuedBytesEnd = 0U;
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privateHandle->dmaDescriptorsUsed = 0U;
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privateHandle->descriptor = 0U;
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privateHandle->queueDescriptor = 0U;
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privateHandle->intA = false;
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}
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void I2S_RxTransferCreateHandleDMA(I2S_Type *base,
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i2s_dma_handle_t *handle,
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dma_handle_t *dmaHandle,
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i2s_dma_transfer_callback_t callback,
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void *userData)
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{
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I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData);
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}
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status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
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{
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status_t status;
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I2S_DisableDMAInterrupts(handle);
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/* Enqueue transfer buffer */
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status = I2S_EnqueueUserBuffer(base, handle, transfer);
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if (status != kStatus_Success)
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{
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I2S_EnableDMAInterrupts(handle);
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return status;
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}
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/* Initialize DMA transfer */
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if (handle->state == kI2S_DmaStateIdle)
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{
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handle->state = kI2S_DmaStateRx;
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status = I2S_StartTransferDMA(base, handle);
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if (status != kStatus_Success)
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{
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I2S_EnableDMAInterrupts(handle);
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return status;
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}
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}
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I2S_AddTransferDMA(base, handle);
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I2S_EnableDMAInterrupts(handle);
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return kStatus_Success;
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}
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static void I2S_TxEnableDMA(I2S_Type *base, bool enable)
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{
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if (enable)
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{
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base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK;
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}
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else
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{
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base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK);
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base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK;
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}
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}
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static void I2S_RxEnableDMA(I2S_Type *base, bool enable)
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{
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if (enable)
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{
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base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK;
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}
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else
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{
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base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK);
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base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK;
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}
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}
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static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer)
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{
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assert(transfer);
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uint16_t transferBytes;
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if (transfer->dataSize >= (2 * DMA_MAX_TRANSFER_BYTES))
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{
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transferBytes = DMA_MAX_TRANSFER_BYTES;
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}
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else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES)
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{
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transferBytes = transfer->dataSize / 2U;
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if ((transferBytes % 4U) != 0U)
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{
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transferBytes -= (transferBytes % 4U);
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}
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}
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else
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{
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transferBytes = transfer->dataSize;
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}
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return transferBytes;
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}
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static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
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{
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status_t status;
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dma_transfer_config_t xferConfig = {0};
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i2s_dma_private_handle_t *privateHandle;
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volatile i2s_transfer_t *transfer;
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uint16_t transferBytes;
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uint32_t instance;
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int i;
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dma_descriptor_t *descriptor;
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dma_descriptor_t *nextDescriptor;
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dma_xfercfg_t xfercfg;
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instance = I2S_GetInstance(base);
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privateHandle = &(s_DmaPrivateHandle[instance]);
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transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]);
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transferBytes = I2S_GetTransferBytes(transfer);
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/* Prepare transfer of data via initial DMA transfer descriptor */
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DMA_PrepareTransfer(
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&xferConfig, (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t)(&(base->FIFORD))),
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(void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)(&(base->FIFOWR)) : (uint32_t)transfer->data), sizeof(uint32_t),
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transferBytes, (handle->state == kI2S_DmaStateTx) ? kDMA_MemoryToPeripheral : kDMA_PeripheralToMemory,
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(void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U]));
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/* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */
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privateHandle->dmaDescriptorsUsed = 1U;
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privateHandle->intA = false;
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privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes;
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privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS;
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transfer->dataSize -= transferBytes;
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transfer->data += transferBytes;
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if (transfer->dataSize == 0U)
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{
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transfer->data = NULL;
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privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS;
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}
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/* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes */
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for (i = 0; i < DMA_DESCRIPTORS; i++)
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{
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descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]);
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nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1) % DMA_DESCRIPTORS)]);
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xfercfg.valid = true;
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xfercfg.reload = true;
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xfercfg.swtrig = false;
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xfercfg.clrtrig = false;
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xfercfg.intA = false;
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xfercfg.intB = false;
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xfercfg.byteWidth = sizeof(uint32_t);
|
|
xfercfg.srcInc = 0U;
|
|
xfercfg.dstInc = 0U;
|
|
xfercfg.transferCount = 8U;
|
|
|
|
DMA_CreateDescriptor(descriptor, &xfercfg,
|
|
((handle->state == kI2S_DmaStateTx) ? (void *)&s_DummyBufferTx : (void *)(uint32_t)(&(base->FIFORD))),
|
|
((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)(&(base->FIFOWR)) : (void *)&s_DummyBufferRx),
|
|
(void *)nextDescriptor);
|
|
}
|
|
|
|
/* Submit and start initial DMA transfer */
|
|
|
|
if (handle->state == kI2S_DmaStateTx)
|
|
{
|
|
I2S_TxEnableDMA(base, true);
|
|
}
|
|
else
|
|
{
|
|
I2S_RxEnableDMA(base, true);
|
|
}
|
|
|
|
status = DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
|
|
if (status != kStatus_Success)
|
|
{
|
|
return status;
|
|
}
|
|
|
|
DMA_StartTransfer(handle->dmaHandle);
|
|
|
|
I2S_Enable(base);
|
|
return kStatus_Success;
|
|
}
|
|
|
|
static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
|
|
{
|
|
dma_xfercfg_t xfercfg;
|
|
volatile i2s_transfer_t *transfer;
|
|
uint16_t transferBytes;
|
|
uint32_t instance;
|
|
i2s_dma_private_handle_t *privateHandle;
|
|
dma_descriptor_t *descriptor;
|
|
dma_descriptor_t *nextDescriptor;
|
|
uint32_t srcAddr = 0, destAddr = 0;
|
|
|
|
instance = I2S_GetInstance(base);
|
|
privateHandle = &(s_DmaPrivateHandle[instance]);
|
|
|
|
while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS)
|
|
{
|
|
transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]);
|
|
|
|
if (transfer->dataSize == 0U)
|
|
{
|
|
/* Nothing to be added */
|
|
return;
|
|
}
|
|
|
|
/* Determine currently configured descriptor and the other which it will link to */
|
|
descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]);
|
|
privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS;
|
|
nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]);
|
|
|
|
transferBytes = I2S_GetTransferBytes(transfer);
|
|
privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes;
|
|
privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS;
|
|
|
|
/* Configure descriptor */
|
|
|
|
xfercfg.valid = true;
|
|
xfercfg.reload = true;
|
|
xfercfg.swtrig = false;
|
|
xfercfg.clrtrig = false;
|
|
xfercfg.intA = privateHandle->intA;
|
|
xfercfg.intB = !privateHandle->intA;
|
|
xfercfg.byteWidth = sizeof(uint32_t);
|
|
xfercfg.srcInc = (handle->state == kI2S_DmaStateTx) ? 1U : 0U;
|
|
xfercfg.dstInc = (handle->state == kI2S_DmaStateTx) ? 0U : 1U;
|
|
xfercfg.transferCount = transferBytes / sizeof(uint32_t);
|
|
srcAddr = ((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t)&(base->FIFORD));
|
|
destAddr = ((handle->state == kI2S_DmaStateTx) ? (uint32_t)&(base->FIFOWR) : (uint32_t)transfer->data);
|
|
|
|
DMA_CreateDescriptor(descriptor, &xfercfg, (void *)srcAddr, (void *)destAddr, (void *)nextDescriptor);
|
|
|
|
/* Advance internal state */
|
|
|
|
privateHandle->dmaDescriptorsUsed++;
|
|
privateHandle->intA = !privateHandle->intA;
|
|
|
|
transfer->dataSize -= transferBytes;
|
|
transfer->data += transferBytes;
|
|
if (transfer->dataSize == 0U)
|
|
{
|
|
transfer->data = NULL;
|
|
privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS;
|
|
}
|
|
}
|
|
}
|
|
|
|
void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds)
|
|
{
|
|
i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData;
|
|
i2s_dma_handle_t *i2sHandle = privateHandle->handle;
|
|
I2S_Type *base = privateHandle->base;
|
|
|
|
if ((!transferDone) || (i2sHandle->state == kI2S_DmaStateIdle))
|
|
{
|
|
return;
|
|
}
|
|
|
|
if (privateHandle->dmaDescriptorsUsed > 0U)
|
|
{
|
|
/* Finished descriptor, decrease amount of data to be processed */
|
|
|
|
i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize -=
|
|
privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
|
|
i2sHandle->i2sQueue[i2sHandle->queueDriver].data +=
|
|
privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
|
|
privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U;
|
|
privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS;
|
|
|
|
privateHandle->dmaDescriptorsUsed--;
|
|
|
|
if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
|
|
{
|
|
/* Entire user buffer sent or received - advance to next one */
|
|
i2sHandle->i2sQueue[i2sHandle->queueDriver].data = NULL;
|
|
i2sHandle->queueDriver = (i2sHandle->queueDriver + 1U) % I2S_NUM_BUFFERS;
|
|
|
|
/* Notify user about buffer completion */
|
|
if (i2sHandle->completionCallback)
|
|
{
|
|
(i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
|
|
{
|
|
/* All user buffers processed */
|
|
I2S_TransferAbortDMA(base, i2sHandle);
|
|
|
|
/* Notify user about completion of the final buffer */
|
|
if (i2sHandle->completionCallback)
|
|
{
|
|
(i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_Done, i2sHandle->userData);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */
|
|
I2S_AddTransferDMA(base, i2sHandle);
|
|
}
|
|
}
|