104 lines
2.7 KiB
C
104 lines
2.7 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2019 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_gpc.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.gpc_1"
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#endif
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/*!
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* brief Enable the IRQ.
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*
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* param base GPC peripheral base address.
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* param irqId ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms.
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*/
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void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId)
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{
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uint32_t irqRegNum = irqId / 32U;
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uint32_t irqRegShiftNum = irqId % 32U;
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assert(irqRegNum <= GPC_IMR_COUNT);
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#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31)
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if (irqRegNum == GPC_IMR_COUNT)
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{
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base->IMR5 &= ~(1UL << irqRegShiftNum);
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}
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else
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{
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base->IMR[irqRegNum] &= ~(1UL << irqRegShiftNum);
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}
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#else
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assert(irqRegNum > 0U);
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base->IMR[irqRegNum - 1UL] &= ~(1UL << irqRegShiftNum);
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#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
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}
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/*!
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* brief Disable the IRQ.
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*
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* param base GPC peripheral base address.
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* param irqId ID number of IRQ to be disabled, available range is 32-159. 0-31 is available in some platforms.
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*/
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void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId)
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{
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uint32_t irqRegNum = irqId / 32U;
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uint32_t irqRegShiftNum = irqId % 32U;
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assert(irqRegNum <= GPC_IMR_COUNT);
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#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31)
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if (irqRegNum == GPC_IMR_COUNT)
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{
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base->IMR5 |= (1UL << irqRegShiftNum);
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}
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else
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{
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base->IMR[irqRegNum] |= (1UL << irqRegShiftNum);
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}
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#else
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assert(irqRegNum > 0U);
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base->IMR[irqRegNum - 1UL] |= (1UL << irqRegShiftNum);
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#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
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}
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/*!
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* brief Get the IRQ/Event flag.
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*
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* param base GPC peripheral base address.
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* param irqId ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms.
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* return Indicated IRQ/Event is asserted or not.
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*/
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bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId)
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{
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uint32_t irqRegNum = irqId / 32U;
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uint32_t irqRegShiftNum = irqId % 32U;
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uint32_t ret;
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assert(irqRegNum <= GPC_IMR_COUNT);
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#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31)
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if (irqRegNum == GPC_IMR_COUNT)
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{
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ret = base->ISR5 & (1UL << irqRegShiftNum);
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}
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else
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{
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ret = base->ISR[irqRegNum] & (1UL << irqRegShiftNum);
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}
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#else
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assert(irqRegNum > 0U);
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ret = base->ISR[irqRegNum - 1UL] & (1UL << irqRegShiftNum);
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#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
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return (1UL << irqRegShiftNum) == ret;
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}
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