2168ed8e7d
PCI/PCIe have better performance and more devices support, such as NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by IOMMU that the virtualiztion and userspace driver will more safety. PCI/PCIe device could hot plugging, no design modifications SoC required, PCI/PCIe on Embedded SoC is popular now. We make a simple framework to support them. Feature Lists: 1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC. 2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC. 3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework. 4.Endpoint: a simple EP framework for PCI FPGA or NTB function. 5.OFW: we only support work on OFW SoC, ACPI support in the future maybe. Host controller: 1. Common PCI host controller on ECAM. 2. Generic PCI host controller on ECAM. Signed-off-by: GuEe-GUI <2991707448@qq.com>
73 lines
1.7 KiB
C
73 lines
1.7 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-24 GuEe-GUI first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#define DBG_TAG "pci.ecam"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#include "ecam.h"
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struct pci_ecam_config_window *pci_ecam_create(struct rt_pci_host_bridge *host_bridge,
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const struct pci_ecam_ops *ops)
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{
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struct pci_ecam_config_window *conf_win = rt_calloc(1, sizeof(*conf_win));
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if (!conf_win)
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{
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return RT_NULL;
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}
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conf_win->bus_range = host_bridge->bus_range;
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conf_win->bus_shift = ops->bus_shift;
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conf_win->ops = ops;
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host_bridge->ops = (const struct rt_pci_ops *)&ops->pci_ops;
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return conf_win;
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}
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void *pci_ecam_map(struct rt_pci_bus *bus, rt_uint32_t devfn, int where)
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{
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struct pci_ecam_config_window *conf_win = bus->sysdata;
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const struct pci_ecam_ops *eops = conf_win->ops;
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void *win = conf_win->win, *map;
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rt_uint32_t busn = bus->number, bus_shift = eops->bus_shift, devfn_shift = bus_shift - 8;
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busn -= conf_win->bus_range[0];
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if (bus_shift)
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{
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rt_uint32_t bus_offset = (busn & PCIE_ECAM_BUS_MASK) << bus_shift;
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rt_uint32_t devfn_offset = (devfn & PCIE_ECAM_DEVFN_MASK) << devfn_shift;
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where &= PCIE_ECAM_REG_MASK;
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map = win + (bus_offset | devfn_offset | where);
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}
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else
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{
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map = win + PCIE_ECAM_OFFSET(busn, devfn, where);
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}
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return map;
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}
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const struct pci_ecam_ops pci_generic_ecam_ops =
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{
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.pci_ops =
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{
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.map = pci_ecam_map,
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.read = rt_pci_bus_read_config_uxx,
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.write = rt_pci_bus_write_config_uxx,
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}
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};
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