153 lines
4.2 KiB
C
153 lines
4.2 KiB
C
/**************************************************************************//**
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*
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* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-02-22 klcheng First version
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*
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******************************************************************************/
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#include "NuMicro.h"
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#include <rtdevice.h>
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#include <drv_gpio.h>
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#if defined(BOARD_USING_STORAGE_SPIFLASH)
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#if defined(RT_USING_SFUD)
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#include "spi_flash.h"
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#include "spi_flash_sfud.h"
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#endif
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#include "drv_qspi.h"
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#define W25X_REG_READSTATUS (0x05)
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#define W25X_REG_READSTATUS2 (0x35)
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#define W25X_REG_WRITEENABLE (0x06)
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#define W25X_REG_WRITESTATUS (0x01)
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#define W25X_REG_QUADENABLE (0x02)
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static rt_uint8_t SpiFlash_ReadStatusReg(struct rt_qspi_device *qspi_device)
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{
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rt_uint8_t u8Val;
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rt_err_t result = RT_EOK;
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rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS;
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result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
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RT_ASSERT(result > 0);
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return u8Val;
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}
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static rt_uint8_t SpiFlash_ReadStatusReg2(struct rt_qspi_device *qspi_device)
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{
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rt_uint8_t u8Val;
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rt_err_t result = RT_EOK;
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rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS2;
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result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
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RT_ASSERT(result > 0);
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return u8Val;
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}
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static rt_err_t SpiFlash_WriteStatusReg(struct rt_qspi_device *qspi_device, uint8_t u8Value1, uint8_t u8Value2)
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{
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rt_uint8_t w25x_txCMD1;
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rt_uint8_t au8Val[2];
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rt_err_t result;
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struct rt_qspi_message qspi_message = {0};
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/* Enable WE */
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w25x_txCMD1 = W25X_REG_WRITEENABLE;
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result = rt_qspi_send(qspi_device, &w25x_txCMD1, sizeof(w25x_txCMD1));
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if (result != sizeof(w25x_txCMD1))
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goto exit_SpiFlash_WriteStatusReg;
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/* Prepare status-1, 2 data */
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au8Val[0] = u8Value1;
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au8Val[1] = u8Value2;
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/* 1-bit mode: Instruction+payload */
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qspi_message.instruction.content = W25X_REG_WRITESTATUS;
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qspi_message.instruction.qspi_lines = 1;
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qspi_message.qspi_data_lines = 1;
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qspi_message.parent.cs_take = 1;
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qspi_message.parent.cs_release = 1;
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qspi_message.parent.send_buf = &au8Val[0];
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qspi_message.parent.length = sizeof(au8Val);
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qspi_message.parent.next = RT_NULL;
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if (rt_qspi_transfer_message(qspi_device, &qspi_message) != sizeof(au8Val))
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{
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result = -RT_ERROR;
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}
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result = RT_EOK;
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exit_SpiFlash_WriteStatusReg:
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return result;
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}
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static void SpiFlash_WaitReady(struct rt_qspi_device *qspi_device)
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{
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volatile uint8_t u8ReturnValue;
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do
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{
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u8ReturnValue = SpiFlash_ReadStatusReg(qspi_device);
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u8ReturnValue = u8ReturnValue & 1;
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}
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while (u8ReturnValue != 0); // check the BUSY bit
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}
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static void SpiFlash_EnterQspiMode(struct rt_qspi_device *qspi_device)
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{
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rt_err_t result = RT_EOK;
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uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
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uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
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u8Status2 |= W25X_REG_QUADENABLE;
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result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
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RT_ASSERT(result == RT_EOK);
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SpiFlash_WaitReady(qspi_device);
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}
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static void SpiFlash_ExitQspiMode(struct rt_qspi_device *qspi_device)
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{
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rt_err_t result = RT_EOK;
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uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
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uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
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u8Status2 &= ~W25X_REG_QUADENABLE;
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result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
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RT_ASSERT(result == RT_EOK);
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SpiFlash_WaitReady(qspi_device);
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}
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static int rt_hw_spiflash_init(void)
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{
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/* Here, we use Dual I/O to drive the SPI flash by default. */
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/* If you want to use Quad I/O, you can modify to 4 from 2 and crossover D2/D3 pin of SPI flash. */
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if (nu_qspi_bus_attach_device("qspi0", "qspi01", 2, SpiFlash_EnterQspiMode, SpiFlash_ExitQspiMode) != RT_EOK)
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return -1;
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#if defined(RT_USING_SFUD)
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if (rt_sfud_flash_probe("flash0", "qspi01") == RT_NULL)
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{
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return -(RT_ERROR);
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}
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#endif
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return 0;
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}
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INIT_COMPONENT_EXPORT(rt_hw_spiflash_init);
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#endif /* BOARD_USING_STORAGE_SPIFLASH */
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