210 lines
8.4 KiB
C
210 lines
8.4 KiB
C
/*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*/
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/******************************************************************************/
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/** \file hc32f460_timer0.h
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**
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** A detailed description is available at
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** @link Timer0Group description @endlink
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**
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** - 2018-10-11 CDT First version for Device Driver Library of TIMER0.
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**
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******************************************************************************/
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#ifndef __HC32F460_TIMER0_H__
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#define __HC32F460_TIMER0_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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#if (DDL_TIMER0_ENABLE == DDL_ON)
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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*******************************************************************************
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** \defgroup Timer0Group Timer0
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**
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******************************************************************************/
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//@{
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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*******************************************************************************
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** \brief Timer0 channel enumeration
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**
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******************************************************************************/
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typedef enum en_tim0_channel
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{
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Tim0_ChannelA = 0x00u,
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Tim0_ChannelB = 0x01u
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}en_tim0_channel_t;
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/**
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*******************************************************************************
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** \brief Timer0 Async Mode clock enumeration
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**
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******************************************************************************/
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typedef enum en_tim0_async_clock_src
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{
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Tim0_LRC = 0x00u,
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Tim0_XTAL32 = 0x01u
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}en_tim0_async_clock_src_t;
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/**
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*******************************************************************************
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** \brief Timer0 Sync Mode clock enumeration
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**
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******************************************************************************/
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typedef enum en_tim0_sync_clock_src
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{
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Tim0_Pclk1 = 0x00u,
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Tim0_InsideHardTrig = 0x01u
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}en_tim0_sync_clock_src_t;
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/**
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*******************************************************************************
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** \brief Timer0 counter mode enumeration
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**
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******************************************************************************/
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typedef enum en_tim0_counter_mode
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{
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Tim0_Sync = 0x00u,
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Tim0_Async = 0x01u
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}en_tim0_counter_mode_t;
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/**
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*******************************************************************************
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** \brief Timer0 trigger event mode enumeration
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**
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******************************************************************************/
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typedef enum en_tim0_function
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{
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Tim0_OutputCapare = 0x00u,
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Tim0_InputCaptrue = 0x01u
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}en_tim0_function_t;
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/**
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*******************************************************************************
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** \brief Timer0 clock division enumeration
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**
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******************************************************************************/
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typedef enum en_tim0_clock_div
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{
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Tim0_ClkDiv0 = 0u,
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Tim0_ClkDiv2,
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Tim0_ClkDiv4,
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Tim0_ClkDiv8,
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Tim0_ClkDiv16,
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Tim0_ClkDiv32,
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Tim0_ClkDiv64,
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Tim0_ClkDiv128,
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Tim0_ClkDiv256,
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Tim0_ClkDiv512,
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Tim0_ClkDiv1024
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}en_tim0_clock_div_t;
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/**
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*******************************************************************************
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** \brief Timer0 common trigger source select enumeration
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**
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******************************************************************************/
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typedef enum en_tim0_com_trigger
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{
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Tim0ComTrigger_1 = 1u, ///< Select common trigger 1.
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Tim0ComTrigger_2 = 2u, ///< Select common trigger 2.
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Tim0ComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2.
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} en_tim0_com_trigger_t;
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/**
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*******************************************************************************
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** \brief Timer0 trigger function init structrue definition
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**
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******************************************************************************/
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typedef struct stc_tim0_trigger_init
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{
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en_tim0_function_t Tim0_OCMode; ///<specifies the TIM mode value of @ref en_tim0_function_t
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en_event_src_t Tim0_SelTrigSrc; ///<specifies the TIM Clk Src, and this parameter can be a value of @ref en_event_src_t
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bool Tim0_InTrigEnable;///<specifies the TIM enable trigger
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bool Tim0_InTrigClear; ///<specifies the TIM enable trigger clear
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bool Tim0_InTrigStop; ///<specifies the TIM enable trigger stop
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bool Tim0_InTrigStart; ///<specifies the TIM enable trigger start
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}stc_tim0_trigger_init_t;
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/**
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*******************************************************************************
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** \brief Timer0 base counter function init structrue definition
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**
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******************************************************************************/
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typedef struct stc_tim0_base_init
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{
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en_tim0_clock_div_t Tim0_ClockDivision; ///<specifies the TIM clock division, and this parameter can be a value of @ref en_tim0_clock_div_t*/
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en_tim0_sync_clock_src_t Tim0_SyncClockSource; ///<specifies the TIM sync clock source, and this parameter can be a value of @ref en_tim0_sync_clock_src_t*/
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en_tim0_async_clock_src_t Tim0_AsyncClockSource;///<specifies the TIM async clock source, and this parameter can be a value of @ref en_tim0_async_clock_src_t*/
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en_tim0_counter_mode_t Tim0_CounterMode; ///<specifies the TIM counter mode, and this parameter can be a value of @ref en_tim0_counter_mode_t*/
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uint16_t Tim0_CmpValue; ///<specifies the TIM counter value This value can be set 0-0xFFFF
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}stc_tim0_base_init_t;
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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en_flag_status_t TIMER0_GetFlag(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh);
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en_result_t TIMER0_ClearFlag(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh);
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en_result_t TIMER0_Cmd(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh,
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en_functional_state_t enCmd);
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en_result_t TIMER0_SetFunc(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh,
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en_tim0_function_t enFunc);
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en_result_t TIMER0_IntCmd(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh,
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en_functional_state_t enCmd);
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uint16_t TIMER0_GetCntReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh);
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en_result_t TIMER0_WriteCntReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh,uint16_t u16Cnt);
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uint16_t TIMER0_GetCmpReg(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh);
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en_result_t TIMER0_WriteCmpReg(M4_TMR0_TypeDef* pstcTim0Reg, en_tim0_channel_t enCh,uint16_t u16Cnt);
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en_result_t TIMER0_BaseInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh,
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const stc_tim0_base_init_t* pstcBaseInit);
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en_result_t TIMER0_DeInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh);
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en_result_t TIMER0_HardTriggerInit(M4_TMR0_TypeDef* pstcTim0Reg,en_tim0_channel_t enCh,
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const stc_tim0_trigger_init_t* pStcInit);
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void TIMER0_SetTriggerSrc(en_event_src_t enEvent);
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void TIMER0_ComTriggerCmd(en_tim0_com_trigger_t enComTrigger, en_functional_state_t enState);
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//@} // Timer0Group
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#ifdef __cplusplus
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}
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#endif
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#endif /* DDL_TIMER0_ENABLE */
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#endif /* __HC32F460_TIMER0_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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