d8aa99a29c
* the initial support of synopsys designware arc processor * the initial support of synospsy ARC EM Starter Kit * the bsp code is based on embarc which is a common SDK for all synopsys ARC-based boards * use "scons --gdb" to debug emsk with em9d configuration * for detailed board information, pls go embarc.org Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
30 lines
891 B
C
30 lines
891 B
C
/*
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* Copyright (c) 2018, Synopsys, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MUX_HAL_H_
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#define _MUX_HAL_H_
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/**
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* \name Mux Control Register Index
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* @{
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*/
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#define PMOD_MUX_CTRL 0 /*!< 32-bits, offset 0x0,
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This register controls mapping of the peripheral device signals on Pmod connectors */
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#define I2C_MAP_CTRL 1 /*!< 32-bits, offset 0x4 */
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#define SPI_MAP_CTRL 2 /*!< 32-bits, offset 0x8,
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SPI_MAP_CTRL[0] selects the mode of operation of the SPI Slave:
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- Normal operation, SPI_MAP_CTRL[0]=0: SPI Slave is connected to Pmod1 at connector J1.
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- Loop-back mode, SPI_MAP_CTRL[0]=1: SPI Slave is connected to the SPI Master inside the FPGA using CS4.
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*/
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#define UART_MAP_CTRL 3 /*!< 32-bits, offset 0x8,
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This register controls the mapping of the UART signals on the Pmod1 connector. */
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/** @} end of name */
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#endif /* _MUX_HAL_H_ */
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