728 lines
19 KiB
C
728 lines
19 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-05-23 liuduanfei first version
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* 2020-08-25 wanghaijing add sdmmmc2
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* 2023-03-26 wdfk-prog Distinguish between SDMMC and SDIO drivers
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*/
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#include "board.h"
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#ifdef RT_USING_SDIO
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#if !defined(BSP_USING_SDIO1) && !defined(BSP_USING_SDIO2)
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#error "Please define at least one BSP_USING_SDIOx"
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#endif
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#include "drv_sdmmc.h"
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#define DBG_TAG "drv.sdmmc"
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#ifdef DRV_DEBUG
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#define DBG_LVL DBG_LOG
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#else
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#define DBG_LVL DBG_INFO
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#endif /* DRV_DEBUG */
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#include <rtdbg.h>
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static struct stm32_sdio_class sdio_obj;
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static struct rt_mmcsd_host *host1;
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static struct rt_mmcsd_host *host2;
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#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (1000000)
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#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
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#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
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struct sdio_pkg
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{
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struct rt_mmcsd_cmd *cmd;
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void *buff;
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rt_uint32_t flag;
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};
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struct rthw_sdio
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{
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struct rt_mmcsd_host *host;
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struct stm32_sdio_des sdio_des;
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struct rt_event event;
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struct rt_mutex mutex;
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struct sdio_pkg *pkg;
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};
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rt_align(SDIO_ALIGN_LEN)
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static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
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/**
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* @brief This function get order from sdio.
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* @param data
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* @retval sdio order
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*/
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static int get_order(rt_uint32_t data)
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{
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int order = 0;
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switch (data)
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{
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case 1:
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order = 0;
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break;
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case 2:
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order = 1;
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break;
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case 4:
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order = 2;
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break;
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case 8:
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order = 3;
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break;
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case 16:
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order = 4;
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break;
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case 32:
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order = 5;
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break;
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case 64:
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order = 6;
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break;
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case 128:
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order = 7;
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break;
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case 256:
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order = 8;
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break;
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case 512:
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order = 9;
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break;
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case 1024:
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order = 10;
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break;
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case 2048:
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order = 11;
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break;
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case 4096:
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order = 12;
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break;
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case 8192:
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order = 13;
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break;
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case 16384:
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order = 14;
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break;
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default :
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order = 0;
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break;
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}
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return order;
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}
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/**
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* @brief This function wait sdio cmd completed.
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* @param sdio rthw_sdio
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* @retval None
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*/
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static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
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{
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rt_uint32_t status;
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struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
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struct rt_mmcsd_data *data = cmd->data;
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SD_TypeDef *hsd = sdio->sdio_des.hw_sdio.Instance;
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if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
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rt_tick_from_millisecond(5000), &status) != RT_EOK)
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{
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LOG_E("wait cmd completed timeout");
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cmd->err = -RT_ETIMEOUT;
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return;
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}
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if (sdio->pkg == RT_NULL)
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{
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return;
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}
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/* Get Card Specific Data */
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cmd->resp[0] = hsd->RESP1;
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if (resp_type(cmd) == RESP_R2)
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{
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cmd->resp[1] = hsd->RESP2;
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cmd->resp[2] = hsd->RESP3;
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cmd->resp[3] = hsd->RESP4;
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}
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/* Check for error conditions */
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if (status & SDIO_ERRORS)
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{
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if ((status & SDMMC_STA_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
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{
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cmd->err = RT_EOK;
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}
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else
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{
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cmd->err = -RT_ERROR;
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}
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}
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else
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{
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cmd->err = RT_EOK;
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}
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if (status & SDMMC_IT_CTIMEOUT)
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{
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cmd->err = -RT_ETIMEOUT;
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}
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if (status & SDMMC_IT_DCRCFAIL)
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{
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data->err = -RT_ERROR;
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}
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if (status & SDMMC_IT_DTIMEOUT)
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{
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data->err = -RT_ETIMEOUT;
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}
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if (cmd->err == RT_EOK)
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{
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LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
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}
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else
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{
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LOG_D("err:0x%08x, %s%s%s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d",
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status,
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status & HW_SDIO_IT_CCRCFAIL ? "CCRCFAIL " : "",
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status & HW_SDIO_IT_DCRCFAIL ? "DCRCFAIL " : "",
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status & HW_SDIO_IT_CTIMEOUT ? "CTIMEOUT " : "",
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status & HW_SDIO_IT_DTIMEOUT ? "DTIMEOUT " : "",
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status & HW_SDIO_IT_TXUNDERR ? "TXUNDERR " : "",
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status & HW_SDIO_IT_RXOVERR ? "RXOVERR " : "",
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status == 0 ? "NULL" : "",
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cmd->cmd_code,
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cmd->arg,
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data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
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data ? data->blks * data->blksize : 0,
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data ? data->blksize : 0
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);
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}
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}
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/**
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* @brief This function send command.
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* @param sdio rthw_sdio
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* @param pkg sdio package
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* @retval None
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*/
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static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
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{
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struct rt_mmcsd_cmd *cmd = pkg->cmd;
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struct rt_mmcsd_data *data = cmd->data;
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SD_TypeDef *hsd = sdio->sdio_des.hw_sdio.Instance;
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rt_uint32_t reg_cmd;
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rt_event_control(&sdio->event, RT_IPC_CMD_RESET, RT_NULL);
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/* save pkg */
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sdio->pkg = pkg;
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LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n",
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cmd->cmd_code,
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cmd->arg,
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resp_type(cmd) == RESP_NONE ? "NONE" : "",
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resp_type(cmd) == RESP_R1 ? "R1" : "",
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resp_type(cmd) == RESP_R1B ? "R1B" : "",
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resp_type(cmd) == RESP_R2 ? "R2" : "",
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resp_type(cmd) == RESP_R3 ? "R3" : "",
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resp_type(cmd) == RESP_R4 ? "R4" : "",
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resp_type(cmd) == RESP_R5 ? "R5" : "",
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resp_type(cmd) == RESP_R6 ? "R6" : "",
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resp_type(cmd) == RESP_R7 ? "R7" : "",
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data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
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data ? data->blks * data->blksize : 0,
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data ? data->blksize : 0
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);
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/* open irq */
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__HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDIO_MASKR_ALL);
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reg_cmd = cmd->cmd_code | SDMMC_CMD_CPSMEN;
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/* data pre configuration */
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if (data != RT_NULL)
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{
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SCB_CleanInvalidateDCache();
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reg_cmd |= SDMMC_CMD_CMDTRANS;
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__HAL_SD_DISABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_MASK_CMDRENDIE | SDMMC_MASK_CMDSENTIE);
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hsd->DTIMER = HW_SDIO_DATATIMEOUT;
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hsd->DLEN = data->blks * data->blksize;
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hsd->DCTRL = (get_order(data->blksize) << 4) | (data->flags & DATA_DIR_READ ? SDMMC_DCTRL_DTDIR : 0);
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hsd->IDMABASE0 = (rt_uint32_t)cache_buf;
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hsd->IDMACTRL = SDMMC_IDMA_IDMAEN;
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}
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/* config cmd reg */
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if (resp_type(cmd) == RESP_NONE)
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reg_cmd |= SDMMC_RESPONSE_NO;
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else if (resp_type(cmd) == RESP_R2)
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reg_cmd |= SDMMC_RESPONSE_LONG;
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else
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reg_cmd |= SDMMC_RESPONSE_SHORT;
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hsd->ARG = cmd->arg;
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hsd->CMD = reg_cmd;
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/* wait completed */
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rthw_sdio_wait_completed(sdio);
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/* Waiting for data to be sent to completion */
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if (data != RT_NULL)
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{
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volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS;
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while (count && (hsd->STA & SDMMC_STA_DPSMACT))
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{
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count--;
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}
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if ((count == 0) || (hsd->STA & SDIO_ERRORS))
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{
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cmd->err = -RT_ERROR;
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}
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}
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/* data post configuration */
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if (data != RT_NULL)
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{
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if (data->flags & DATA_DIR_READ)
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{
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rt_memcpy(data->buf, cache_buf, data->blks * data->blksize);
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SCB_CleanInvalidateDCache();
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}
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}
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}
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/**
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* @brief This function send sdio request.
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* @param sdio rthw_sdio
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* @param req request
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* @retval None
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*/
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static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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{
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struct sdio_pkg pkg;
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struct rthw_sdio *sdio = host->private_data;
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struct rt_mmcsd_data *data;
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RTHW_SDIO_LOCK(sdio);
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if (req->cmd != RT_NULL)
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{
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rt_memset(&pkg, 0, sizeof(pkg));
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data = req->cmd->data;
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pkg.cmd = req->cmd;
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if (data != RT_NULL)
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{
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rt_uint32_t size = data->blks * data->blksize;
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RT_ASSERT(size <= SDIO_BUFF_SIZE);
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if (data->flags & DATA_DIR_WRITE)
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{
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rt_memcpy(cache_buf, data->buf, size);
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}
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}
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rthw_sdio_send_command(sdio, &pkg);
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}
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if (req->stop != RT_NULL)
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{
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rt_memset(&pkg, 0, sizeof(pkg));
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pkg.cmd = req->stop;
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rthw_sdio_send_command(sdio, &pkg);
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}
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RTHW_SDIO_UNLOCK(sdio);
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mmcsd_req_complete(sdio->host);
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}
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/**
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* @brief This function config sdio.
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* @param host rt_mmcsd_host
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* @param io_cfg rt_mmcsd_io_cfg
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* @retval None
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*/
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static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
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{
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rt_uint32_t temp, clk_src;
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rt_uint32_t clk = io_cfg->clock;
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struct rthw_sdio *sdio = host->private_data;
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SD_HandleTypeDef *hsd = &sdio->sdio_des.hw_sdio;
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SDMMC_InitTypeDef Init = {0};
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rt_uint32_t sdmmc_clk = sdio->sdio_des.clk_get();
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if (sdmmc_clk < 400 * 1000)
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{
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LOG_E("The clock rate is too low! rata:%d", sdmmc_clk);
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return;
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}
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if (clk > host->freq_max)
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clk = host->freq_max;
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if (clk > sdmmc_clk)
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{
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LOG_W("Setting rate is greater than clock source rate.");
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clk = sdmmc_clk;
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}
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LOG_D("clk:%dK width:%s%s%s power:%s%s%s",
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clk / 1000,
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io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
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io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
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io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
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io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
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io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
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io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""
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);
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if (sdmmc_clk != 0U)
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{
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hsd->Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ);
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/* Configure the SDMMC peripheral */
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Init.ClockEdge = hsd->Init.ClockEdge;
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Init.ClockPowerSave = hsd->Init.ClockPowerSave;
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if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
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{
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Init.BusWide = SDMMC_BUS_WIDE_4B;
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}
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else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
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{
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Init.BusWide = SDMMC_BUS_WIDE_8B;
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}
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else
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{
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Init.BusWide = SDMMC_BUS_WIDE_1B;
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}
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Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
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/* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
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if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ)))
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{
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Init.ClockDiv = hsd->Init.ClockDiv;
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}
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//CARD_ULTRA_HIGH_SPEED :UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards and <104Mo/s for SDR104, Spec version 3.01
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else if (MMCSD_TIMING_UHS_SDR50 <= io_cfg->timing && io_cfg->timing <= MMCSD_TIMING_UHS_DDR50)
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{
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/* UltraHigh speed SD card,user Clock div */
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Init.ClockDiv = hsd->Init.ClockDiv;
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}
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//CARD_HIGH_SPEED: High Speed Card <25Mo/s , Spec version 2.00
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else if (io_cfg->timing == MMCSD_TIMING_SD_HS)
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{
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/* High speed SD card, Max Frequency = 50Mhz */
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if (hsd->Init.ClockDiv == 0U)
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{
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if (sdmmc_clk > SD_HIGH_SPEED_FREQ)
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{
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Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
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}
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else
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{
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Init.ClockDiv = hsd->Init.ClockDiv;
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}
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}
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else
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{
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if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ)
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{
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Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
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}
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else
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{
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Init.ClockDiv = hsd->Init.ClockDiv;
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}
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}
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}
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//CARD_NORMAL_SPEED: Normal Speed Card <12.5Mo/s , Spec Version 1.01
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else if (io_cfg->timing == MMCSD_TIMING_LEGACY)
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{
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/* No High speed SD card, Max Frequency = 25Mhz */
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if (hsd->Init.ClockDiv == 0U)
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{
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if (sdmmc_clk > SD_NORMAL_SPEED_FREQ)
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{
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Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
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}
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else
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{
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Init.ClockDiv = hsd->Init.ClockDiv;
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}
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}
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else
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{
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if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ)
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{
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Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
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}
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else
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{
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Init.ClockDiv = hsd->Init.ClockDiv;
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}
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}
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}
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(void)SDMMC_Init(hsd->Instance, Init);
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}
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switch ((io_cfg->power_mode)&0X03)
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{
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case MMCSD_POWER_OFF:
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/* Set Power State to OFF */
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(void)SDMMC_PowerState_OFF(hsd->Instance);
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break;
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case MMCSD_POWER_UP:
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/* In F4 series chips, 0X01 is reserved bit and has no practical effect.
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For F7 series chips, 0X01 is power-on after power-off,The SDMMC disables the function and the card clock stops.
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For H7 series chips, 0X03 is the power-on function.
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*/
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case MMCSD_POWER_ON:
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/* Set Power State to ON */
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(void)SDMMC_PowerState_ON(hsd->Instance);
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break;
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default:
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LOG_W("unknown power mode %d", io_cfg->power_mode);
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break;
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}
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}
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/**
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* @brief This function update sdio interrupt.
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* @param host rt_mmcsd_host
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* @param enable
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* @retval None
|
|
*/
|
|
void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
|
|
{
|
|
struct rthw_sdio *sdio = host->private_data;
|
|
|
|
if (enable)
|
|
{
|
|
LOG_D("enable sdio irq");
|
|
__HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_IT_SDIOIT);
|
|
}
|
|
else
|
|
{
|
|
LOG_D("disable sdio irq");
|
|
__HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_IT_SDIOIT);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief This function detect sdcard.
|
|
* @param host rt_mmcsd_host
|
|
* @retval 0x01
|
|
*/
|
|
static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host)
|
|
{
|
|
LOG_D("try to detect device");
|
|
return 0x01;
|
|
}
|
|
|
|
/**
|
|
* @brief This function interrupt process function.
|
|
* @param host rt_mmcsd_host
|
|
* @retval None
|
|
*/
|
|
void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
|
|
{
|
|
struct rthw_sdio *sdio = host->private_data;
|
|
rt_uint32_t intstatus = sdio->sdio_des.hw_sdio.Instance->STA;
|
|
|
|
/* clear irq flag*/
|
|
__HAL_SD_CLEAR_FLAG(&sdio->sdio_des.hw_sdio, intstatus);
|
|
rt_event_send(&sdio->event, intstatus);
|
|
}
|
|
|
|
static const struct rt_mmcsd_host_ops ops =
|
|
{
|
|
rthw_sdio_request,
|
|
rthw_sdio_iocfg,
|
|
rthw_sd_detect,
|
|
rthw_sdio_irq_update,
|
|
};
|
|
|
|
/**
|
|
* @brief This function create mmcsd host.
|
|
* @param sdio_des stm32_sdio_des
|
|
* @retval rt_mmcsd_host
|
|
*/
|
|
struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des)
|
|
{
|
|
struct rt_mmcsd_host *host;
|
|
struct rthw_sdio *sdio = RT_NULL;
|
|
|
|
if (sdio_des == RT_NULL)
|
|
{
|
|
LOG_E("L:%d F:%s",(sdio_des == RT_NULL ? "sdio_des is NULL" : ""));
|
|
return RT_NULL;
|
|
}
|
|
|
|
sdio = rt_malloc(sizeof(struct rthw_sdio));
|
|
|
|
if (sdio == RT_NULL)
|
|
{
|
|
LOG_E("L:%d F:%s malloc rthw_sdio fail");
|
|
return RT_NULL;
|
|
}
|
|
|
|
rt_memset(sdio, 0, sizeof(struct rthw_sdio));
|
|
|
|
host = mmcsd_alloc_host();
|
|
|
|
if (host == RT_NULL)
|
|
{
|
|
LOG_E("L:%d F:%s mmcsd alloc host fail");
|
|
rt_free(sdio);
|
|
return RT_NULL;
|
|
}
|
|
|
|
rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des));
|
|
#ifdef BSP_USING_SDIO1
|
|
if(sdio_des->hw_sdio.Instance == SDMMC1)
|
|
{
|
|
rt_event_init(&sdio->event, "sdio1", RT_IPC_FLAG_FIFO);
|
|
rt_mutex_init(&sdio->mutex, "sdio1", RT_IPC_FLAG_PRIO);
|
|
}
|
|
#endif /* BSP_USING_SDIO1 */
|
|
#ifdef BSP_USING_SDIO2
|
|
if(sdio_des->hw_sdio.Instance == SDMMC2)
|
|
{
|
|
rt_event_init(&sdio->event, "sdio2", RT_IPC_FLAG_FIFO);
|
|
rt_mutex_init(&sdio->mutex, "sdio2", RT_IPC_FLAG_PRIO);
|
|
}
|
|
#endif /* BSP_USING_SDIO2 */
|
|
|
|
/* set host default attributes */
|
|
host->ops = &ops;
|
|
host->freq_min = 400 * 1000;
|
|
host->freq_max = SDIO_MAX_FREQ;
|
|
host->valid_ocr = 0X00FFFF80;/* The voltage range supported is 1.65v-3.6v */
|
|
|
|
#ifndef SDIO_USING_1_BIT
|
|
host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED;
|
|
#else
|
|
host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
|
|
#endif
|
|
host->max_seg_size = SDIO_BUFF_SIZE;
|
|
host->max_dma_segs = 1;
|
|
host->max_blk_size = 512;
|
|
host->max_blk_count = 512;
|
|
|
|
/* link up host and sdio */
|
|
sdio->host = host;
|
|
host->private_data = sdio;
|
|
|
|
rthw_sdio_irq_update(host, 1);
|
|
|
|
/* ready to change */
|
|
mmcsd_change(host);
|
|
|
|
return host;
|
|
}
|
|
|
|
/**
|
|
* @brief This function get stm32 sdio clock.
|
|
* @param hw_sdio: stm32_sdio
|
|
* @retval PCLK2Freq
|
|
*/
|
|
static rt_uint32_t stm32_sdio_clock_get(void)
|
|
{
|
|
return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
|
|
}
|
|
|
|
void SDMMC1_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
/* Process All SDIO Interrupt Sources */
|
|
rthw_sdio_irq_process(host1);
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void SDMMC2_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
/* Process All SDIO Interrupt Sources */
|
|
rthw_sdio_irq_process(host2);
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
int rt_hw_sdio_init(void)
|
|
{
|
|
#ifdef BSP_USING_SDIO1
|
|
struct stm32_sdio_des sdio_des1 = {0};
|
|
sdio_des1.hw_sdio.Instance = SDMMC1;
|
|
|
|
HAL_SD_MspInit(&sdio_des1.hw_sdio);
|
|
HAL_NVIC_SetPriority(SDMMC1_IRQn, 2, 0);
|
|
HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
|
|
|
|
sdio_des1.clk_get = stm32_sdio_clock_get;
|
|
|
|
host1 = sdio_host_create(&sdio_des1);
|
|
|
|
if (host1 == RT_NULL)
|
|
{
|
|
LOG_E("host1 create fail");
|
|
return -RT_ERROR;
|
|
}
|
|
#endif /* BSP_USING_SDIO1 */
|
|
|
|
#ifdef BSP_USING_SDIO2
|
|
struct stm32_sdio_des sdio_des2 = {0};
|
|
sdio_des2.hw_sdio.Instance = SDMMC2;
|
|
|
|
HAL_SD_MspInit(&sdio_des2.hw_sdio);
|
|
HAL_NVIC_SetPriority(SDMMC2_IRQn, 2, 0);
|
|
HAL_NVIC_EnableIRQ(SDMMC2_IRQn);
|
|
|
|
sdio_des2.clk_get = stm32_sdio_clock_get;
|
|
|
|
host2 = sdio_host_create(&sdio_des2);
|
|
|
|
if (host2 == RT_NULL)
|
|
{
|
|
LOG_E("host2 create fail");
|
|
return -RT_ERROR;
|
|
}
|
|
#endif /* BSP_USING_SDIO2 */
|
|
return RT_EOK;
|
|
}
|
|
INIT_DEVICE_EXPORT(rt_hw_sdio_init);
|
|
|
|
void stm32_mmcsd_change(void)
|
|
{
|
|
#ifdef BSP_USING_SDIO1
|
|
mmcsd_change(host1);
|
|
#endif /* BSP_USING_SDIO2 */
|
|
#ifdef BSP_USING_SDIO2
|
|
mmcsd_change(host2);
|
|
#endif /* BSP_USING_SDIO2 */
|
|
}
|
|
|
|
#endif /* RT_USING_SDIO */
|