425 lines
12 KiB
ArmAsm
425 lines
12 KiB
ArmAsm
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-03-19 WangHuachen first version
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*/
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.equ Mode_USR, 0x10
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.equ Mode_FIQ, 0x11
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.equ Mode_IRQ, 0x12
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.equ Mode_SVC, 0x13
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.equ Mode_ABT, 0x17
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.equ Mode_UND, 0x1B
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.equ Mode_SYS, 0x1F
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.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
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.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
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.equ UND_Stack_Size, 0x00000000
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.equ SVC_Stack_Size, 0x00000000
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.equ ABT_Stack_Size, 0x00000000
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.equ FIQ_Stack_Size, 0x00000200
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.equ IRQ_Stack_Size, 0x00000200
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.equ USR_Stack_Size, 0x00000000
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.set RPU_GLBL_CNTL, 0xFF9A0000
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.set RPU_ERR_INJ, 0xFF9A0020
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.set RPU_0_CFG, 0xFF9A0100
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.set RPU_1_CFG, 0xFF9A0200
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.set RST_LPD_DBG, 0xFF5E0240
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.set BOOT_MODE_USER, 0xFF5E0200
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.set fault_log_enable, 0x101
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#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
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FIQ_Stack_Size + IRQ_Stack_Size)
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.section .data.share.isr
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/* stack */
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.globl stack_start
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.globl stack_top
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.align 3
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.bss
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stack_start:
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.rept ISR_Stack_Size
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.long 0
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.endr
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stack_top:
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.section .boot,"axS"
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/* reset entry */
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.globl _reset
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_reset:
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/* Initialize processor registers to 0 */
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mov r0,#0
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mov r1,#0
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mov r2,#0
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mov r3,#0
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mov r4,#0
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mov r5,#0
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mov r6,#0
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mov r7,#0
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mov r8,#0
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mov r9,#0
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mov r10,#0
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mov r11,#0
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mov r12,#0
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/* set the cpu to SVC32 mode and disable interrupt */
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cpsid if, #Mode_SVC
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/* setup stack */
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bl stack_setup
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/*
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* Enable access to VFP by enabling access to Coprocessors 10 and 11.
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* Enables Full Access i.e. in both privileged and non privileged modes
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*/
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mrc p15, 0, r0, c1, c0, 2 /* Read Coprocessor Access Control Register (CPACR) */
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orr r0, r0, #(0xF << 20) /* Enable access to CP 10 & 11 */
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mcr p15, 0, r0, c1, c0, 2 /* Write Coprocessor Access Control Register (CPACR) */
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isb
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/* enable fpu access */
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vmrs r3, FPEXC
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orr r1, r3, #(1<<30)
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vmsr FPEXC, r1
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/* clear the floating point register*/
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mov r1,#0
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vmov d0,r1,r1
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vmov d1,r1,r1
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vmov d2,r1,r1
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vmov d3,r1,r1
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vmov d4,r1,r1
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vmov d5,r1,r1
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vmov d6,r1,r1
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vmov d7,r1,r1
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vmov d8,r1,r1
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vmov d9,r1,r1
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vmov d10,r1,r1
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vmov d11,r1,r1
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vmov d12,r1,r1
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vmov d13,r1,r1
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vmov d14,r1,r1
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vmov d15,r1,r1
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#ifdef __SOFTFP__
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/* Disable the FPU if SOFTFP is defined*/
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vmsr FPEXC,r3
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#endif
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/* Disable MPU and caches */
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mrc p15, 0, r0, c1, c0, 0 /* Read CP15 Control Register*/
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bic r0, r0, #0x05 /* Disable MPU (M bit) and data cache (C bit) */
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bic r0, r0, #0x1000 /* Disable instruction cache (I bit) */
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dsb /* Ensure all previous loads/stores have completed */
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mcr p15, 0, r0, c1, c0, 0 /* Write CP15 Control Register */
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isb /* Ensure subsequent insts execute wrt new MPU settings */
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/* Disable Branch prediction, TCM ECC checks */
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mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR */
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orr r0, r0, #(0x1 << 17) /* Enable RSDIS bit 17 to disable the return stack */
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orr r0, r0, #(0x1 << 16) /* Clear BP bit 15 and set BP bit 16:*/
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bic r0, r0, #(0x1 << 15) /* Branch always not taken and history table updates disabled*/
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orr r0, r0, #(0x1 << 27) /* Enable B1TCM ECC check */
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orr r0, r0, #(0x1 << 26) /* Enable B0TCM ECC check */
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orr r0, r0, #(0x1 << 25) /* Enable ATCM ECC check */
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bic r0, r0, #(0x1 << 5) /* Generate abort on parity errors, with [5:3]=b 000*/
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bic r0, r0, #(0x1 << 4)
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bic r0, r0, #(0x1 << 3)
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mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
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dsb /* Complete all outstanding explicit memory operations*/
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/* Invalidate caches */
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mov r0,#0 /* r0 = 0 */
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dsb
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mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
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mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/
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isb
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/* enable fault log for lock step */
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ldr r0,=RPU_GLBL_CNTL
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ldr r1, [r0]
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ands r1, r1, #0x8
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/* branch to initialization if split mode*/
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bne init
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/* check for boot mode if in lock step, branch to init if JTAG boot mode*/
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ldr r0,=BOOT_MODE_USER
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ldr r1, [r0]
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ands r1, r1, #0xF
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beq init
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/* reset the debug logic */
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ldr r0,=RST_LPD_DBG
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ldr r1, [r0]
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orr r1, r1, #(0x1 << 4)
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orr r1, r1, #(0x1 << 5)
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str r1, [r0]
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/* enable fault log */
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ldr r0,=RPU_ERR_INJ
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ldr r1,=fault_log_enable
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ldr r2, [r0]
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orr r2, r2, r1
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str r2, [r0]
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nop
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nop
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init:
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bl Init_MPU /* Initialize MPU */
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/* Enable Branch prediction */
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mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
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bic r0, r0, #(0x1 << 17) /* Clear RSDIS bit 17 to enable return stack*/
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bic r0, r0, #(0x1 << 16) /* Clear BP bit 15 and BP bit 16:*/
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bic r0, r0, #(0x1 << 15) /* Normal operation, BP is taken from the global history table.*/
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orr r0, r0, #(0x1 << 14) /* Disable DBWR for errata 780125 */
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mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
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/* Enable icahce and dcache */
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mrc p15,0,r1,c1,c0,0
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ldr r0, =0x1005
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orr r1,r1,r0
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dsb
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mcr p15,0,r1,c1,c0,0 /* Enable cache */
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isb /* isb flush prefetch buffer */
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/* Set vector table in TCM/LOVEC */
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mrc p15, 0, r0, c1, c0, 0
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mvn r1, #0x2000
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and r0, r0, r1
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mcr p15, 0, r0, c1, c0, 0
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/* Clear VINITHI to enable LOVEC on reset */
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#if 1
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ldr r0, =RPU_0_CFG
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#else
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ldr r0, =RPU_1_CFG
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#endif
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ldr r1, [r0]
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bic r1, r1, #(0x1 << 2)
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str r1, [r0]
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/* enable asynchronous abort exception */
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mrs r0, cpsr
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bic r0, r0, #0x100
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msr cpsr_xsf, r0
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/* clear .bss */
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mov r0,#0 /* get a zero */
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ldr r1,=__bss_start /* bss start */
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ldr r2,=__bss_end /* bss end */
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bss_loop:
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cmp r1,r2 /* check if data to clear */
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strlo r0,[r1],#4 /* clear 4 bytes */
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blo bss_loop /* loop until done */
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/* call C++ constructors of global objects */
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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ctor_loop:
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cmp r0, r1
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beq ctor_end
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ldr r2, [r0], #4
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stmfd sp!, {r0-r1}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r1}
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b ctor_loop
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ctor_end:
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/* start RT-Thread Kernel */
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ldr pc, _entry
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_entry:
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.word entry
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stack_setup:
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ldr r0, =stack_top
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@ Set the startup stack for svc
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mov sp, r0
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@ Enter Undefined Instruction Mode and set its Stack Pointer
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msr cpsr_c, #Mode_UND|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #UND_Stack_Size
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@ Enter Abort Mode and set its Stack Pointer
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msr cpsr_c, #Mode_ABT|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #ABT_Stack_Size
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@ Enter FIQ Mode and set its Stack Pointer
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msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #FIQ_Stack_Size
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@ Enter IRQ Mode and set its Stack Pointer
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msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #IRQ_Stack_Size
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@ Switch back to SVC
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msr cpsr_c, #Mode_SVC|I_Bit|F_Bit
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bx lr
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.section .text.isr, "ax"
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/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */
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.align 5
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.globl vector_fiq
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vector_fiq:
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stmfd sp!,{r0-r7,lr}
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bl rt_hw_trap_fiq
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ldmfd sp!,{r0-r7,lr}
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subs pc,lr,#4
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.globl rt_interrupt_enter
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.globl rt_interrupt_leave
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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.align 5
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.globl vector_irq
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vector_irq:
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stmfd sp!, {r0-r12,lr}
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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vstmdb sp!, {d0-d15} /* Store floating point registers */
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vmrs r1, FPSCR
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stmfd sp!,{r1}
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vmrs r1, FPEXC
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stmfd sp!,{r1}
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#endif
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bl rt_interrupt_enter
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bl rt_hw_trap_irq
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bl rt_interrupt_leave
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@ if rt_thread_switch_interrupt_flag set, jump to
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@ rt_hw_context_switch_interrupt_do and don't return
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ldr r0, =rt_thread_switch_interrupt_flag
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ldr r1, [r0]
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cmp r1, #1
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beq rt_hw_context_switch_interrupt_do
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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ldmfd sp!, {r1} /* Restore floating point registers */
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vmsr FPEXC, r1
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ldmfd sp!, {r1}
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vmsr FPSCR, r1
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vldmia sp!, {d0-d15}
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#endif
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ldmfd sp!, {r0-r12,lr}
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subs pc, lr, #4
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rt_hw_context_switch_interrupt_do:
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mov r1, #0 @ clear flag
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str r1, [r0]
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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ldmfd sp!, {r1} /* Restore floating point registers */
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vmsr FPEXC, r1
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ldmfd sp!, {r1}
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vmsr FPSCR, r1
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vldmia sp!, {d0-d15}
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#endif
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mov r1, sp @ r1 point to {r0-r3} in stack
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add sp, sp, #4*4
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ldmfd sp!, {r4-r12,lr}@ reload saved registers
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mrs r0, spsr @ get cpsr of interrupt thread
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sub r2, lr, #4 @ save old task's pc to r2
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@ Switch to SVC mode with no interrupt.
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msr cpsr_c, #I_Bit|F_Bit|Mode_SVC
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stmfd sp!, {r2} @ push old task's pc
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stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4
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ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread
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stmfd sp!, {r1-r4} @ push old task's r0-r3
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stmfd sp!, {r0} @ push old task's cpsr
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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vstmdb sp!, {d0-d15} /* Store floating point registers */
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vmrs r1, FPSCR
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stmfd sp!,{r1}
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vmrs r1, FPEXC
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stmfd sp!,{r1}
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#endif
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ldr r4, =rt_interrupt_from_thread
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ldr r5, [r4]
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str sp, [r5] @ store sp in preempted tasks's TCB
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ldr r6, =rt_interrupt_to_thread
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ldr r7, [r6]
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ldr sp, [r7] @ get new task's stack pointer
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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ldmfd sp!, {r1} /* Restore floating point registers */
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vmsr FPEXC, r1
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ldmfd sp!, {r1}
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vmsr FPSCR, r1
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vldmia sp!, {d0-d15}
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#endif
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ldmfd sp!, {r4} @ pop new task's cpsr to spsr
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msr spsr_cxsf, r4
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ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
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.macro push_svc_reg
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sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */
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stmia sp, {r0 - r12} @/* Calling r0-r12 */
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mov r0, sp
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mrs r6, spsr @/* Save CPSR */
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str lr, [r0, #15*4] @/* Push PC */
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str r6, [r0, #16*4] @/* Push CPSR */
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cps #Mode_SVC
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str sp, [r0, #13*4] @/* Save calling SP */
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str lr, [r0, #14*4] @/* Save calling PC */
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.endm
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.align 5
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.globl vector_swi
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vector_swi:
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push_svc_reg
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bl rt_hw_trap_swi
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b .
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.align 5
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.globl vector_undef
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vector_undef:
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push_svc_reg
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bl rt_hw_trap_undef
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b .
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.align 5
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.globl vector_pabt
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vector_pabt:
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push_svc_reg
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bl rt_hw_trap_pabt
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b .
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.align 5
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.globl vector_dabt
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vector_dabt:
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push_svc_reg
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bl rt_hw_trap_dabt
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b .
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.align 5
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.globl vector_resv
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vector_resv:
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push_svc_reg
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bl rt_hw_trap_resv
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b .
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