665 lines
18 KiB
C
665 lines
18 KiB
C
/**************************************************************************//**
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* @file core_cmFunc.h
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* @brief CMSIS Cortex-M Core Function Access Header File
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* @version V2.03
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* @date 07. April 2011
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*
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* @note
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* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifndef __CORE_CMFUNC_H__
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#define __CORE_CMFUNC_H__
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/* ########################### Core Function Access ########################### */
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/** \ingroup CMSIS_Core_FunctionInterface
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\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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@{
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*/
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#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
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/* ARM armcc specific functions */
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/* intrinsic void __enable_irq(); */
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/* intrinsic void __disable_irq(); */
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/** \brief Get Control Register
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This function returns the content of the Control Register.
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\return Control Register value
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_CONTROL(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_CONTROL(void)
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{
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register uint32_t __regControl __ASM("control");
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return(__regControl);
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}
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#endif /* __ARMCC_VERSION */
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/** \brief Set Control Register
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This function writes the given value to the Control Register.
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\param [in] control Control Register value to set
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*/
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#if (__ARMCC_VERSION < 400000)
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extern void __set_CONTROL(uint32_t control);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE void __set_CONTROL(uint32_t control)
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{
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register uint32_t __regControl __ASM("control");
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__regControl = control;
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}
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#endif /* __ARMCC_VERSION */
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/** \brief Get ISPR Register
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This function returns the content of the ISPR Register.
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\return ISPR Register value
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_IPSR(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_IPSR(void)
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{
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register uint32_t __regIPSR __ASM("ipsr");
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return(__regIPSR);
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}
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#endif /* __ARMCC_VERSION */
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/** \brief Get APSR Register
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This function returns the content of the APSR Register.
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\return APSR Register value
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_APSR(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_APSR(void)
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{
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register uint32_t __regAPSR __ASM("apsr");
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return(__regAPSR);
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}
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#endif /* __ARMCC_VERSION */
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/** \brief Get xPSR Register
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This function returns the content of the xPSR Register.
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\return xPSR Register value
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_xPSR(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_xPSR(void)
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{
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register uint32_t __regXPSR __ASM("xpsr");
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return(__regXPSR);
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}
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#endif /* __ARMCC_VERSION */
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/** \brief Get Process Stack Pointer
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This function returns the current value of the Process Stack Pointer (PSP).
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\return PSP Register value
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_PSP(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_PSP(void)
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{
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register uint32_t __regProcessStackPointer __ASM("psp");
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return(__regProcessStackPointer);
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}
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#endif /* __ARMCC_VERSION */
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/** \brief Set Process Stack Pointer
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This function assigns the given value to the Process Stack Pointer (PSP).
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\param [in] topOfProcStack Process Stack Pointer value to set
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*/
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#if (__ARMCC_VERSION < 400000)
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extern void __set_PSP(uint32_t topOfProcStack);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE void __set_PSP(uint32_t topOfProcStack)
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{
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register uint32_t __regProcessStackPointer __ASM("psp");
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__regProcessStackPointer = topOfProcStack;
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}
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#endif /* __ARMCC_VERSION */
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/** \brief Get Main Stack Pointer
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This function returns the current value of the Main Stack Pointer (MSP).
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\return MSP Register value
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_MSP(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_MSP(void)
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{
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register uint32_t __regMainStackPointer __ASM("msp");
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return(__regMainStackPointer);
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}
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#endif /* __ARMCC_VERSION */
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/** \brief Set Main Stack Pointer
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This function assigns the given value to the Main Stack Pointer (MSP).
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\param [in] topOfMainStack Main Stack Pointer value to set
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*/
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#if (__ARMCC_VERSION < 400000)
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extern void __set_MSP(uint32_t topOfMainStack);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE void __set_MSP(uint32_t topOfMainStack)
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{
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register uint32_t __regMainStackPointer __ASM("msp");
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__regMainStackPointer = topOfMainStack;
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}
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#endif /* __ARMCC_VERSION */
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/** \brief Get Priority Mask
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This function returns the current state of the priority mask bit from the Priority Mask Register.
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\return Priority Mask value
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_PRIMASK(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_PRIMASK(void)
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{
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register uint32_t __regPriMask __ASM("primask");
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return(__regPriMask);
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}
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#endif /* __ARMCC_VERSION */
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/** \brief Set Priority Mask
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This function assigns the given value to the Priority Mask Register.
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\param [in] priMask Priority Mask
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*/
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#if (__ARMCC_VERSION < 400000)
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extern void __set_PRIMASK(uint32_t priMask);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE void __set_PRIMASK(uint32_t priMask)
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{
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register uint32_t __regPriMask __ASM("primask");
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__regPriMask = (priMask);
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}
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#endif /* __ARMCC_VERSION */
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#if (__CORTEX_M >= 0x03)
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/** \brief Enable FIQ
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This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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#define __enable_fault_irq __enable_fiq
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/** \brief Disable FIQ
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This function disables FIQ interrupts by setting the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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#define __disable_fault_irq __disable_fiq
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/** \brief Get Base Priority
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This function returns the current value of the Base Priority register.
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\return Base Priority register value
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_BASEPRI(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_BASEPRI(void)
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{
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register uint32_t __regBasePri __ASM("basepri");
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return(__regBasePri);
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}
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#endif /* __ARMCC_VERSION */
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/** \brief Set Base Priority
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This function assigns the given value to the Base Priority register.
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\param [in] basePri Base Priority value to set
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*/
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#if (__ARMCC_VERSION < 400000)
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extern void __set_BASEPRI(uint32_t basePri);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE void __set_BASEPRI(uint32_t basePri)
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{
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register uint32_t __regBasePri __ASM("basepri");
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__regBasePri = (basePri & 0xff);
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}
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#endif /* __ARMCC_VERSION */
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/** \brief Get Fault Mask
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This function returns the current value of the Fault Mask register.
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\return Fault Mask register value
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_FAULTMASK(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_FAULTMASK(void)
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{
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register uint32_t __regFaultMask __ASM("faultmask");
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return(__regFaultMask);
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}
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#endif /* __ARMCC_VERSION */
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/** \brief Set Fault Mask
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This function assigns the given value to the Fault Mask register.
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\param [in] faultMask Fault Mask value to set
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*/
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#if (__ARMCC_VERSION < 400000)
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extern void __set_FAULTMASK(uint32_t faultMask);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE void __set_FAULTMASK(uint32_t faultMask)
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{
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register uint32_t __regFaultMask __ASM("faultmask");
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__regFaultMask = (faultMask & 1);
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}
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#endif /* __ARMCC_VERSION */
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#endif /* (__CORTEX_M >= 0x03) */
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#if (__CORTEX_M == 0x04)
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/** \brief Get FPSCR
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This function returns the current value of the Floating Point Status/Control register.
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\return Floating Point Status/Control register value
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*/
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static __INLINE uint32_t __get_FPSCR(void)
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{
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#if (__FPU_PRESENT == 1)
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register uint32_t __regfpscr __ASM("fpscr");
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return(__regfpscr);
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#else
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return(0);
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#endif
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}
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/** \brief Set FPSCR
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This function assigns the given value to the Floating Point Status/Control register.
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\param [in] fpscr Floating Point Status/Control value to set
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*/
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static __INLINE void __set_FPSCR(uint32_t fpscr)
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{
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#if (__FPU_PRESENT == 1)
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register uint32_t __regfpscr __ASM("fpscr");
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__regfpscr = (fpscr);
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#endif
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}
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#endif /* (__CORTEX_M == 0x04) */
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#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
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/* IAR iccarm specific functions */
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#include <cmsis_iar.h>
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#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
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/* GNU gcc specific functions */
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/** \brief Enable IRQ Interrupts
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This function enables IRQ interrupts by clearing the I-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
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{
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__ASM volatile ("cpsie i");
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}
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/** \brief Disable IRQ Interrupts
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This function disables IRQ interrupts by setting the I-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
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{
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__ASM volatile ("cpsid i");
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}
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/** \brief Get Control Register
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This function returns the content of the Control Register.
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\return Control Register value
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*/
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__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, control" : "=r" (result) );
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return(result);
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}
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/** \brief Set Control Register
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This function writes the given value to the Control Register.
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\param [in] control Control Register value to set
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*/
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__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
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{
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__ASM volatile ("MSR control, %0" : : "r" (control) );
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}
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/** \brief Get ISPR Register
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This function returns the content of the ISPR Register.
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\return ISPR Register value
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*/
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__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
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return(result);
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}
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/** \brief Get APSR Register
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This function returns the content of the APSR Register.
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\return APSR Register value
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*/
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__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, apsr" : "=r" (result) );
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return(result);
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}
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/** \brief Get xPSR Register
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This function returns the content of the xPSR Register.
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\return xPSR Register value
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*/
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__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
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return(result);
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}
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/** \brief Get Process Stack Pointer
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This function returns the current value of the Process Stack Pointer (PSP).
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\return PSP Register value
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*/
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__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
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{
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register uint32_t result;
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__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
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return(result);
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}
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/** \brief Set Process Stack Pointer
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This function assigns the given value to the Process Stack Pointer (PSP).
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\param [in] topOfProcStack Process Stack Pointer value to set
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*/
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__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
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{
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__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
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}
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/** \brief Get Main Stack Pointer
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This function returns the current value of the Main Stack Pointer (MSP).
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\return MSP Register value
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*/
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__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
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{
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register uint32_t result;
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__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
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return(result);
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}
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/** \brief Set Main Stack Pointer
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This function assigns the given value to the Main Stack Pointer (MSP).
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\param [in] topOfMainStack Main Stack Pointer value to set
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*/
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__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
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{
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__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
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}
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/** \brief Get Priority Mask
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This function returns the current state of the priority mask bit from the Priority Mask Register.
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\return Priority Mask value
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*/
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__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, primask" : "=r" (result) );
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return(result);
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}
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/** \brief Set Priority Mask
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This function assigns the given value to the Priority Mask Register.
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\param [in] priMask Priority Mask
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*/
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__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
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{
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__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
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}
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#if (__CORTEX_M >= 0x03)
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/** \brief Enable FIQ
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This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
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{
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__ASM volatile ("cpsie f");
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}
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/** \brief Disable FIQ
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This function disables FIQ interrupts by setting the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
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{
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__ASM volatile ("cpsid f");
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}
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/** \brief Get Base Priority
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This function returns the current value of the Base Priority register.
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\return Base Priority register value
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*/
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__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
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return(result);
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}
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/** \brief Set Base Priority
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This function assigns the given value to the Base Priority register.
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\param [in] basePri Base Priority value to set
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*/
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__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
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{
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__ASM volatile ("MSR basepri, %0" : : "r" (value) );
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}
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/** \brief Get Fault Mask
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|
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This function returns the current value of the Fault Mask register.
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\return Fault Mask register value
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*/
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__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
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|
{
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|
uint32_t result;
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__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
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|
return(result);
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}
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/** \brief Set Fault Mask
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|
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|
This function assigns the given value to the Fault Mask register.
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|
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|
\param [in] faultMask Fault Mask value to set
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|
*/
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|
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
|
{
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|
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
|
}
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#endif /* (__CORTEX_M >= 0x03) */
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#if (__CORTEX_M == 0x04)
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/** \brief Get FPSCR
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|
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|
This function returns the current value of the Floating Point Status/Control register.
|
|
|
|
\return Floating Point Status/Control register value
|
|
*/
|
|
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
|
|
{
|
|
#if (__FPU_PRESENT == 1)
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("MRS %0, fpscr" : "=r" (result) );
|
|
return(result);
|
|
#else
|
|
return(0);
|
|
#endif
|
|
}
|
|
|
|
|
|
/** \brief Set FPSCR
|
|
|
|
This function assigns the given value to the Floating Point Status/Control register.
|
|
|
|
\param [in] fpscr Floating Point Status/Control value to set
|
|
*/
|
|
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
|
|
{
|
|
#if (__FPU_PRESENT == 1)
|
|
__ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
|
|
#endif
|
|
}
|
|
|
|
#endif /* (__CORTEX_M == 0x04) */
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|
|
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|
|
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
|
|
/* TASKING carm specific functions */
|
|
|
|
/*
|
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
|
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
|
* Including the CMSIS ones.
|
|
*/
|
|
|
|
#endif
|
|
|
|
/*@} end of CMSIS_Core_RegAccFunctions */
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|
#endif /* __CORE_CMFUNC_H__ */
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