125 lines
6.8 KiB
C
125 lines
6.8 KiB
C
/*!
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\file gd32f3x0_fwdgt.h
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\brief definitions for the FWDGT
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\version 2017-06-06, V1.0.0, firmware for GD32F3x0
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\version 2019-06-01, V2.0.0, firmware for GD32F3x0
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F3X0_FWDGT_H
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#define GD32F3X0_FWDGT_H
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#include "gd32f3x0.h"
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/* FWDGT definitions */
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#define FWDGT FWDGT_BASE
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/* registers definitions */
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#define FWDGT_CTL REG32(FWDGT + 0x00000000U) /*!< FWDGT control register */
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#define FWDGT_PSC REG32(FWDGT + 0x00000004U) /*!< FWDGT prescaler register */
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#define FWDGT_RLD REG32(FWDGT + 0x00000008U) /*!< FWDGT reload register */
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#define FWDGT_STAT REG32(FWDGT + 0x0000000CU) /*!< FWDGT status register */
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#define FWDGT_WND REG32(FWDGT + 0x00000010U) /*!< FWDGT window register */
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/* bits definitions */
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/* FWDGT_CTL */
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#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
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/* FWDGT_PSC */
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#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
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/* FWDGT_RLD */
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#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
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/* FWDGT_STAT */
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#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
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#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
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#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */
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/* FWDGT_WND */
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#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */
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/* constants definitions */
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/* FWDGT_CTL register value */
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#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_CTL_CMD bit field */
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/* FWDGT_PSC register value */
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#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U))
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#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
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#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
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#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
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#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
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#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
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#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
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#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
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/* FWDGT_RLD register value */
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#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_RLD_RLD bit field */
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/* FWDGT_WND register value */
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#define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_WND_WND bit field */
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/* control value */
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#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
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#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
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#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
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#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
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/* FWDGT timeout value */
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#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */
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#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
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#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
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/* FWDGT flag definitions */
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#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */
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#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */
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#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */
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/* function declarations */
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/* enable write access to FWDGT_PSC and FWDGT_RLD */
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void fwdgt_write_enable(void);
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/* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */
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void fwdgt_write_disable(void);
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/* start the free watchdog timer counter */
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void fwdgt_enable(void);
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/* configure the free watchdog timer counter window value */
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ErrStatus fwdgt_window_value_config(uint16_t window_value);
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/* reload the counter of FWDGT */
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void fwdgt_counter_reload(void);
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/* configure counter reload value, and prescaler divider value */
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ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
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/* get flag state of FWDGT */
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FlagStatus fwdgt_flag_get(uint16_t flag);
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#endif /* GD32F3X0_FWDGT_H */
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